Invention Grant
- Patent Title: Vertically integrated wafers with thermal dissipation
- Patent Title (中): 具有散热的垂直集成晶圆
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Application No.: US14445991Application Date: 2014-07-29
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Publication No.: US09508685B2Publication Date: 2016-11-29
- Inventor: Zhijiong Luo
- Applicant: Empire Technology Development LLC
- Applicant Address: US DE Wilmington
- Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee Address: US DE Wilmington
- Agency: Turk IP Law, LLC
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L21/60 ; H01L25/065 ; H01L23/00 ; H01L21/285 ; H01L21/306 ; H01L21/3065 ; H01L21/822 ; H01L23/36 ; H01L23/532
Abstract:
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.
Public/Granted literature
- US20160035702A1 VERTICALLY INTEGRATED WAFERS WITH THERMAL DISSIPATION Public/Granted day:2016-02-04
Information query
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