Invention Grant
US09508704B2 Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same
有权
制造半导体封装的方法，由此形成的半导体封装以及包括其的半导体器件
- Patent Title: Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same
- Patent Title (中): 制造半导体封装的方法，由此形成的半导体封装以及包括其的半导体器件
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Application No.: US14611585Application Date: 2015-02-02
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Publication No.: US09508704B2Publication Date: 2016-11-29
- Inventor: Hyunsoo Chung , InYoung Lee , Taeje Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-Do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR10-2014-0052581 20140430
- Main IPC: H01L21/34
- IPC: H01L21/34 ; H01L25/00 ; H01L25/065 ; H01L21/768 ; H01L21/306 ; H01L23/00 ; H01L21/56 ; H01L21/304 ; H01L23/31 ; H01L23/538 ; H01L23/498 ; H01L23/29 ; H01L25/10
Abstract:
The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the first side, and the semiconductor wafer including a through via exposed through the first side, forming trenches at cutting areas between chip areas and at edge areas of the semiconductor wafer on the first side, stacking a semiconductor chip on the through via, forming an under fill resin layer to fill a gap between the semiconductor chip and the semiconductor wafer and to cover a side of the semiconductor chip, and forming a molding layer to cover at least a portion of the under fill resin layer and to fill at least a portion of the respective trenches may be provided.
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