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    SEMICONDUCTOR PACKAGE INCLUDING THROUGH-SILICON VIA AND METHOD OF FORMING THE SAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING THROUGH-SILICON VIA AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20230126686A1

    公开(公告)日：2023-04-27

    申请号：US17871449

    申请日：2022-07-22

    申请人： Samsung Electronics Co., Ltd.

    发明人： Inhyo Hwang ,  Younglyong Kim ,  Hyunsoo Chung

    IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    摘要： A semiconductor package includes a package substrate and a plurality of sub-packages provided on the package substrate. Each of the plurality of sub-packages includes a semiconductor chip, an interposer provided adjacent to the semiconductor chip, the interposer including a plurality of first through-silicon vias, an encapsulator provided between the semiconductor chip and the interposer, and a redistribution layer provided on the interposer, the encapsulator and the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite the first surface and a plurality of chip pads provided on the first surface. The redistribution layer includes a plurality of redistribution pads and a horizontal wiring provided between the plurality of redistribution pads and the plurality of first through-silicon vias. The redistribution layer is provided on the second surface of the semiconductor substrate, and extends on the encapsulator and the interposer.

    Semiconductor package and method of manufacturing the same
    2.
    发明授权
    Semiconductor package and method of manufacturing the same 有权

    公开(公告)号：US11362054B2

    公开(公告)日：2022-06-14

    申请号：US16923428

    申请日：2020-07-08

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung

    IPC分类号： H01L23/00

    摘要： A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

    Semiconductor devices having through-electrodes and methods for fabricating the same
    5.
    发明授权
    Semiconductor devices having through-electrodes and methods for fabricating the same 有权
    具有贯通电极的半导体装置及其制造方法

    公开(公告)号：US09355961B2

    公开(公告)日：2016-05-31

    申请号：US14470366

    申请日：2014-08-27

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Chajea Jo ,  Taeje Cho ,  Hyunsoo Chung

    IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

    CPC分类号： H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

    摘要翻译： 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

    Semiconductor package
    6.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12033948B2

    公开(公告)日：2024-07-09

    申请号：US17539963

    申请日：2021-12-01

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

    IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L25/065

    CPC分类号： H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

    摘要： A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.