公开(公告)号：US20250158001A1

公开(公告)日：2025-05-15

申请号：US18780621

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Kwangsoo Kim ,  Chiwoo Lee

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A chip structure including a semiconductor chip, a photonic integrated circuit chip spaced apart from the semiconductor chip in a horizontal direction, an electronic integrated circuit chip on the semiconductor chip and the photonic integrated circuit chip, a first molding layer surrounding the semiconductor chip and the photonic integrated circuit chip, and a second molding layer on the semiconductor chip, the photonic integrated circuit chip, and the first molding layer and surrounding the electronic integrated circuit chip. A portion of the electronic integrated circuit chip overlaps the photonic integrated circuit chip in a vertical direction, and another portion of the electronic integrated circuit chip overlaps the semiconductor chip in the vertical direction.

公开(公告)号：US20250157996A1

公开(公告)日：2025-05-15

申请号：US18814848

申请日：2024-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Chiwoo Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes an interposer substrate including an inorganic material; a first redistribution layer (RDL) on the interposer substrate; a first redistribution structure in the first RDL; a first bonding layer on the first RDL; a first bonding pad in the first bonding layer; a second bonding layer on the first bonding layer; a second bonding pad in the second bonding layer, wherein the second bonding pad contacts the first bonding pad; first semiconductor chips on the second bonding layer, wherein the first semiconductor chips are spaced apart from each other in a horizontal direction; a second RDL on the first semiconductor chips; a second redistribution structure in the second RDL; and second semiconductor chips on the second RDL, wherein the second semiconductor chips are spaced apart from each other in the horizontal direction, and wherein the second semiconductor chips are electrically connected to the second redistribution structure.

公开(公告)号：US20250062237A1

公开(公告)日：2025-02-20

申请号：US18648683

申请日：2024-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangsoo Kim ,  Hyunsoo Chung ,  Jungul Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: Provided is a semiconductor package including a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a circuit board disposed between the first redistribution layer and the first semiconductor chip, bonding wires connecting the first semiconductor chip and the circuit board to each other, a second redistribution layer disposed on the first semiconductor chip, a second semiconductor chip disposed on the second redistribution layer, and conductive posts connecting the first redistribution layer and the second redistribution layer to each other.

公开(公告)号：US20230126686A1

公开(公告)日：2023-04-27

申请号：US17871449

申请日：2022-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhyo Hwang ,  Younglyong Kim ,  Hyunsoo Chung

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate and a plurality of sub-packages provided on the package substrate. Each of the plurality of sub-packages includes a semiconductor chip, an interposer provided adjacent to the semiconductor chip, the interposer including a plurality of first through-silicon vias, an encapsulator provided between the semiconductor chip and the interposer, and a redistribution layer provided on the interposer, the encapsulator and the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite the first surface and a plurality of chip pads provided on the first surface. The redistribution layer includes a plurality of redistribution pads and a horizontal wiring provided between the plurality of redistribution pads and the plurality of first through-silicon vias. The redistribution layer is provided on the second surface of the semiconductor substrate, and extends on the encapsulator and the interposer.

公开(公告)号：US11362054B2

公开(公告)日：2022-06-14

申请号：US16923428

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Taewon Yoo ,  Myungkee Chung

IPC: H01L23/00

Abstract: A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface.

公开(公告)号：US09960112B2

公开(公告)日：2018-05-01

申请号：US15259024

申请日：2016-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Hyunsoo Chung ,  Myeong Soon Park

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14166 ,  H01L2224/16238 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

公开(公告)号：US09853012B2

公开(公告)日：2017-12-26

申请号：US15010438

申请日：2016-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Jongyeon Kim ,  In-Young Lee ,  Tae-Je Cho

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L21/02 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/03 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

公开(公告)号：US09355961B2

公开(公告)日：2016-05-31

申请号：US14470366

申请日：2014-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chajea Jo ,  Taeje Cho ,  Hyunsoo Chung

IPC: H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

Abstract translation: 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

公开(公告)号：US20250054915A1

公开(公告)日：2025-02-13

申请号：US18930667

申请日：2024-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

公开(公告)号：US12033948B2

公开(公告)日：2024-07-09

申请号：US17539963

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.