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    Semiconductor devices having through-electrodes and methods for fabricating the same
    1.
    发明授权
    Semiconductor devices having through-electrodes and methods for fabricating the same 有权
    具有贯通电极的半导体装置及其制造方法

    公开(公告)号：US09355961B2

    公开(公告)日：2016-05-31

    申请号：US14470366

    申请日：2014-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chajea Jo ,  Taeje Cho ,  Hyunsoo Chung

    IPC: H01L23/538 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

    CPC classification number: H01L23/5384 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

    Abstract: A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.

    Abstract translation: 提供了具有贯通电极的半导体器件及其制造方法。 半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一 活性表面 以及被配置为电连接芯片的导电互连。 导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

    Semiconductor package and method of fabricating the same
    5.
    发明授权
    Semiconductor package and method of fabricating the same 有权

    公开(公告)号：US10734367B2

    公开(公告)日：2020-08-04

    申请号：US16232159

    申请日：2018-12-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

    IPC: H01L25/10 ,  H01L23/00 ,  H01L25/03 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

    Stacked-chip packages
    7.
    发明授权
    Stacked-chip packages 有权

    公开(公告)号：US12237319B2

    公开(公告)日：2025-02-25

    申请号：US18418964

    申请日：2024-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daeho Lee ,  Taeje Cho

    IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

    Abstract: A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10121731B2

    公开(公告)日：2018-11-06

    申请号：US15290899

    申请日：2016-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Cheon Park ,  Won Il Lee ,  Chajea Jo ,  Taeje Cho

    IPC: H01L23/48 ,  H01L23/13 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

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