Invention Grant
US09508853B2 Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region
有权
通道包覆最后工艺流程,用于在沟道区中具有减小的尺寸鳍的FinFET器件上形成沟道区
- Patent Title: Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region
- Patent Title (中): 通道包覆最后工艺流程,用于在沟道区中具有减小的尺寸鳍的FinFET器件上形成沟道区
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Application No.: US15073936Application Date: 2016-03-18
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Publication No.: US09508853B2Publication Date: 2016-11-29
- Inventor: Ajey Poovannummoottil Jacob , Witold P. Maszara , Jody A. Fronheiser
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L21/3213 ; H01L21/02 ; H01L29/161 ; H01L29/201 ; H01L21/306 ; H01L29/10 ; H01L29/51

Abstract:
One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.
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