Invention Grant
- Patent Title: High voltage depletion mode N-channel JFET
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Application No.: US14923125Application Date: 2015-10-26
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Publication No.: US09508869B2Publication Date: 2016-11-29
- Inventor: Philip Leland Hower , Sameer Pendharkar , Marie Denison
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/808 ; H01L21/225 ; H01L27/098 ; H01L21/8232 ; H01L29/06 ; H01L21/266 ; H01L29/36 ; H01L29/10 ; H01L21/32 ; H01L29/08
Abstract:
An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
Public/Granted literature
- US20160043236A1 HIGH VOLTAGE DEPLETION MODE N-CHANNEL JFET Public/Granted day:2016-02-11
Information query
IPC分类:
