Invention Grant
- Patent Title: Latency control in a transmitter/receiver buffer
- Patent Title (中): 发送/接收缓冲区中的延迟控制
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Application No.: US14561452Application Date: 2014-12-05
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Publication No.: US09509640B2Publication Date: 2016-11-29
- Inventor: David F. Taylor , Matthew H. Klein , Vincent Vendramini
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent W. Eric Webostad
- Main IPC: H04K1/10
- IPC: H04K1/10 ; G11C7/00 ; H04L12/861 ; H03L7/06 ; G06F5/10 ; G06F5/06 ; H03M9/00 ; G06F5/12

Abstract:
In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.
Public/Granted literature
- US20160164665A1 LATENCY CONTROL IN A TRANSMITTER/RECEIVER BUFFER Public/Granted day:2016-06-09
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