Invention Grant
- Patent Title: Determination of word line to word line shorts between adjacent blocks
- Patent Title (中): 确定字线到相邻块之间的字线短路
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Application No.: US14328070Application Date: 2014-07-10
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Publication No.: US09514835B2Publication Date: 2016-12-06
- Inventor: Sagar Magia , Jagdish Sabde , Khanh Nguyen
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C29/02 ; G11C29/06 ; H01L27/115 ; G11C29/12

Abstract:
A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
Public/Granted literature
- US20160012904A1 Determination of Word Line to Word Line Shorts Between Adjacent Blocks Public/Granted day:2016-01-14
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