中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.085 seconds)

    DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS
    2.
    发明申请
    DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS 有权
    将字线确定为相邻块之间的字线短路

    公开(公告)号：US20170025182A1

    公开(公告)日：2017-01-26

    申请号：US15283645

    申请日：2016-10-03

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Jagdish Sabde ,  Sagar Magia ,  Khanh Nguyen

    IPC: G11C16/34 ,  G11C29/02 ,  G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/3422 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/025 ,  G11C29/06 ,  G11C2029/1202 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

    Abstract translation: 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。

    Time domain ramp rate control for erase inhibit in flash memory
    3.
    发明授权
    Time domain ramp rate control for erase inhibit in flash memory 有权
    闪存中擦除禁止的时域斜率控制

    公开(公告)号：US09490020B2

    公开(公告)日：2016-11-08

    申请号：US15155957

    申请日：2016-05-16

    Applicant: SanDisk Technologies LLC

    Inventor： Kenneth Louie ,  Khanh Nguyen

    IPC: G11C16/04 ,  G11C16/14 ,  G11C16/08

    CPC classification number: G11C16/14 ,  G11C5/146 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32

    Abstract: When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.

    Abstract translation: 当对具有NAND型结构的闪存型非易失性存储器执行擦除时，提出了用于抑制所选字线上的擦除，可选择选择晶体管的选择线或这些的某些组合的技术。 沿着所选择的控制线的电压首先在对应的输入线上斜坡上升，然后通过与阱结构的电容耦合使其电压升高到擦除抑制水平。 这些输入信号的电平随着施加到阱结构的擦除电压而上升，但是基于控制线和阱之间的耦合比的延迟。

    Determination of word line to word line shorts between adjacent blocks
    4.
    发明授权
    Determination of word line to word line shorts between adjacent blocks 有权
    确定字线到相邻块之间的字线短路

    公开(公告)号：US09514835B2

    公开(公告)日：2016-12-06

    申请号：US14328070

    申请日：2014-07-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Sagar Magia ,  Jagdish Sabde ,  Khanh Nguyen

    IPC: G11C16/34 ,  G11C29/02 ,  G11C29/06 ,  H01L27/115 ,  G11C29/12

    CPC classification number: G11C16/3422 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/025 ,  G11C29/06 ,  G11C2029/1202 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

    Abstract translation: 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。

    Dynamic strobe timing
    7.
    发明授权
    Dynamic strobe timing 有权

    公开(公告)号：US10090057B2

    公开(公告)日：2018-10-02

    申请号：US15440940

    申请日：2017-02-23

    Applicant: SanDisk Technologies LLC

    Inventor： Amul Desai ,  Khanh Nguyen

    IPC: G11C7/22 ,  G11C16/32 ,  G11C16/24 ,  G11C7/10

    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic strobe timing. A controller is configured to generate a strobe signal to facilitate data transfer. A controller is configured to receive a feedback signal in response to initiation of a strobe signal. A controller is configured to control a duration of a strobe signal based on a feedback signal.

Patent Agency Ranking