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    Determination of word line to word line shorts between adjacent blocks
    6.
    发明授权
    Determination of word line to word line shorts between adjacent blocks 有权
    确定字线到相邻块之间的字线短路

    公开(公告)号：US09514835B2

    公开(公告)日：2016-12-06

    申请号：US14328070

    申请日：2014-07-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Sagar Magia ,  Jagdish Sabde ,  Khanh Nguyen

    IPC: G11C16/34 ,  G11C29/02 ,  G11C29/06 ,  H01L27/115 ,  G11C29/12

    CPC classification number: G11C16/3422 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/025 ,  G11C29/06 ,  G11C2029/1202 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

    Abstract translation: 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。

    Techniques for determining local interconnect defects
    8.
    发明授权
    Techniques for determining local interconnect defects 有权

    公开(公告)号：US10032524B2

    公开(公告)日：2018-07-24

    申请号：US14712078

    申请日：2015-05-14

    Applicant: SanDisk Technologies LLC

    Inventor： Jagdish Sabde ,  Sagar Magia ,  Jayavel Pachamuthu

    IPC: G11C29/50 ,  G11C29/12 ,  G01R31/04 ,  G11C16/04 ,  G11C29/02 ,  G11C29/06

    Abstract: Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.

    DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS
    9.
    发明申请
    DETERMINATION OF WORD LINE TO WORD LINE SHORTS BETWEEN ADJACENT BLOCKS 有权
    将字线确定为相邻块之间的字线短路

    公开(公告)号：US20170025182A1

    公开(公告)日：2017-01-26

    申请号：US15283645

    申请日：2016-10-03

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Jagdish Sabde ,  Sagar Magia ,  Khanh Nguyen

    IPC: G11C16/34 ,  G11C29/02 ,  G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/3422 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/025 ,  G11C29/06 ,  G11C2029/1202 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

    Abstract translation: 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。

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