发明授权
- 专利标题： Semiconductor packaging structure and forming method therefor
- 专利标题（中）： 半导体封装结构及其形成方法
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申请号： US14780233申请日： 2014-06-26
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公开(公告)号： US09515010B2公开(公告)日： 2016-12-06
- 发明人: Xin Xia , Wanchun Ding , Guohua Gao
- 申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.
- 申请人地址： CN Nantong
- 专利权人： NANTONG FUJITSU MICROELECTRONICS., LTD.
- 当前专利权人： NANTONG FUJITSU MICROELECTRONICS., LTD.
- 当前专利权人地址： CN Nantong
- 代理机构： Harness, Dickey & Pierce, P.L.C.
- 优先权： CN201410061267 20140224; CN201410061904 20140224
- 国际申请： PCT/CN2014/080839 WO 20140626
- 国际公布： WO2015/123952 WO 20150827
- 主分类号： H01L21/44
- IPC分类号： H01L21/44 ; H01L23/495 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L23/29 ; H01L23/00
摘要：
The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins. By adopting the present invention, a transverse area occupied by the package structure is decreased, the volume of the entire package structure is correspondingly decreased, and the integration level of the package structure is improved. The present invention further provides a forming method of the semiconductor package structure.
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