公开(公告)号：US09515010B2

公开(公告)日：2016-12-06

申请号：US14780233

申请日：2014-06-26

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： Xin Xia ,  Wanchun Ding ,  Guohua Gao

IPC分类号： H01L21/44 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L23/49537 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of the chip, the passivation layer is provided with first openings for exposing the bonding pads, and a seed layer connected with the bonding pads and columnar salient points stacked on the seed layer are arranged on the bonding pads; lead frames, wherein each lead frame is provided with a plurality of discrete pins, and internal pins and external pins are respectively arranged on two opposite surfaces of the pins; the chip being flipped on the lead frames, and the columnar salient points being connected with the internal pins; a plastic package layer, wherein the plastic package layer is used for sealing the chip, the columnar salient points and the lead frames and exposing the external pins. By adopting the present invention, a transverse area occupied by the package structure is decreased, the volume of the entire package structure is correspondingly decreased, and the integration level of the package structure is improved. The present invention further provides a forming method of the semiconductor package structure.

摘要翻译： 本发明提供了一种半导体封装结构，包括：芯片，其中，焊盘和钝化层布置在芯片的表面上，钝化层设置有用于暴露焊盘的第一开口，以及与 层叠在种子层上的接合焊盘和柱状突出点配置在接合焊盘上; 引线框架，其中每个引线框架设置有多个分立的引脚，并且内部引脚和外部引脚分别布置在引脚的两个相对表面上; 芯片在引线框架上翻转，柱状突出点与内部引脚连接; 塑料封装层，其中塑料封装层用于密封芯片，柱状突出点和引线框架，并露出外部引脚。 通过采用本发明，封装结构占据的横向面积减小，整体封装结构的体积相应减小，并提高了封装结构的集成度。 本发明还提供一种半导体封装结构的形成方法。