Invention Grant
US09519603B2 Method and apparatus to enable multiple masters to operate in a single master bus architecture
有权
使多个主机能够在单个主总线架构中运行的方法和装置
- Patent Title: Method and apparatus to enable multiple masters to operate in a single master bus architecture
- Patent Title (中): 使多个主机能够在单个主总线架构中运行的方法和装置
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Application No.: US14480540Application Date: 2014-09-08
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Publication No.: US09519603B2Publication Date: 2016-12-13
- Inventor: Shoichiro Sengoku , Richard Dominic Wietfeldt , George Alan Wiley
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: G06F13/378
- IPC: G06F13/378 ; G06F13/36 ; G06F13/24 ; G06F13/362
Abstract:
To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
Public/Granted literature
- US20150074305A1 METHOD AND APPARATUS TO ENABLE MULTIPLE MASTERS TO OPERATE IN A SINGLE MASTER BUS ARCHITECTURE Public/Granted day:2015-03-12
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