发明授权
US09524237B2 Data processing device and semiconductor intergrated circuit device for a bi-endian system
有权
用于双端系统的数据处理设备和半导体集成电路器件
- 专利标题: Data processing device and semiconductor intergrated circuit device for a bi-endian system
- 专利标题(中): 用于双端系统的数据处理设备和半导体集成电路器件
-
申请号: US13063347申请日: 2009-05-28
-
公开(公告)号: US09524237B2公开(公告)日: 2016-12-20
- 发明人: Naoshi Ishikawa , Seiji Ikari , Hiromi Nagayama
- 申请人: Naoshi Ishikawa , Seiji Ikari , Hiromi Nagayama
- 申请人地址: JP Tokyo
- 专利权人: RENESAS ELECTRONICS CORPORATION
- 当前专利权人: RENESAS ELECTRONICS CORPORATION
- 当前专利权人地址: JP Tokyo
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2008-234768 20080912
- 国际申请: PCT/JP2009/059738 WO 20090528
- 国际公布: WO2010/029794 WO 20100318
- 主分类号: G06F12/04
- IPC分类号: G06F12/04 ; G06F9/30
摘要:
The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.
公开/授权文献
信息查询