公开(公告)号：US09524237B2

公开(公告)日：2016-12-20

申请号：US13063347

申请日：2009-05-28

申请人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

发明人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

IPC分类号： G06F12/04 ,  G06F9/30

CPC分类号： G06F12/04 ,  G06F9/30025

摘要： The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

摘要翻译： 本发明提供了一种数据处理装置，其中可以共同使用程序，并且可以共享矢量表，而不管双端系统中的类型如何。 指令固定为小端，用于执行指令的数据的端序是可变的。 向量表中各向量地址的大小为32位，数据访问时的位数最多为32位。 CPU取指令，在执行取指令之前，CPU访问例如存储器中的32位数据。 此时，CPU控制对准器，使得要存储在数据寄存器中的字节单元中的每个地址中的数据的地址和对齐与由指令的小尾数确定的数据的地址和对齐相同，而不依赖于 数据的endian。

公开(公告)号：US08645602B2

公开(公告)日：2014-02-04

申请号：US13179119

申请日：2011-07-08

申请人： Naoshi Ishikawa

发明人： Naoshi Ishikawa

IPC分类号： G06F13/00 ,  H04L27/00

CPC分类号： G06F13/4054

摘要： Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus. Therefore, bus access can be gained irrespective of the magnitude relationship between the frequencies of the CPU and timer.

摘要翻译： 公开了一种可以获得总线访问的微计算机，而不管总线主机的频率与总线从站的频率之间的大小关系如何。 CPU根据具有可变频率的第一时钟进行操作。 定时器根据第二时钟进行操作。 频率转换逻辑电路通过主总线耦合到CPU，并通过外设I / O总线耦合到定时器。 当第一时钟的频率高于第二时钟时，频率转换逻辑电路通过使用第一同步信号产生用于定时器的总线控制信号，该第一同步信号指示用于外围I / O总线的总线控制信号的改变定时 。 当第一时钟的频率低于第二时钟时，频率转换逻辑电路通过使用指示主总线的总线控制信号的改变定时的第二同步信号来产生CPU的总线控制信号。 因此，无论CPU和定时器的频率之间的大小关系如何，都可以获得总线访问。

公开(公告)号：US20120030389A1

公开(公告)日：2012-02-02

申请号：US13179119

申请日：2011-07-08

申请人： Naoshi ISHIKAWA

发明人： Naoshi ISHIKAWA

IPC分类号： G06F13/00

CPC分类号： G06F13/4054

摘要： Disclosed is a microcomputer that can gain bus access irrespective of the magnitude relationship between the frequency of a bus master and the frequency of a bus slave. A CPU operates in accordance a first clock, which has a variable frequency. A timer operates in accordance with a second clock. A frequency conversion logic circuit is coupled to the CPU through a main bus and coupled to the timer through a peripheral I/O bus. When the first clock is higher in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the timer by using a first synchronization signal, which indicates the change timing of a bus control signal for the peripheral I/O bus. When the first clock is lower in frequency than the second clock, the frequency conversion logic circuit generates a bus control signal for the CPU by using a second synchronization signal, which indicates the change timing of a bus control signal for the main bus. Therefore, bus access can be gained irrespective of the magnitude relationship between the frequencies of the CPU and timer.

摘要翻译： 公开了一种可以获得总线访问的微计算机，而不管总线主机的频率与总线从站的频率之间的大小关系如何。 CPU根据具有可变频率的第一时钟进行操作。 定时器根据第二时钟进行操作。 频率转换逻辑电路通过主总线耦合到CPU，并通过外设I / O总线耦合到定时器。 当第一时钟的频率高于第二时钟时，频率转换逻辑电路通过使用第一同步信号产生用于定时器的总线控制信号，该第一同步信号指示用于外围I / O总线的总线控制信号的改变定时 。 当第一时钟的频率低于第二时钟时，频率转换逻辑电路通过使用指示主总线的总线控制信号的改变定时的第二同步信号来产生CPU的总线控制信号。 因此，无论CPU和定时器的频率之间的大小关系如何，都可以获得总线访问。

公开(公告)号：US20110191569A1

公开(公告)日：2011-08-04

申请号：US13063347

申请日：2009-05-28

申请人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

发明人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

IPC分类号： G06F9/315

CPC分类号： G06F12/04 ,  G06F9/30025

摘要： The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

摘要翻译： 本发明提供了一种数据处理装置，其中可以共同使用程序，并且可以共享矢量表，而不管双端系统中的类型如何。 指令固定为小端，用于执行指令的数据的端序是可变的。 向量表中各向量地址的大小为32位，数据访问时的位数最多为32位。 CPU取指令，在执行取指令之前，CPU访问例如存储器中的32位数据。 此时，CPU控制对准器，使得要存储在数据寄存器中的字节单元中的每个地址中的数据的地址和对齐与由指令的小尾数确定的数据的地址和对齐相同，而不依赖于 数据的endian。