利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.014 秒)

    DATA PROCESSING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    DATA PROCESSING DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    数据处理器件和半导体集成电路器件

    公开(公告)号：US20110191569A1

    公开(公告)日：2011-08-04

    申请号：US13063347

    申请日：2009-05-28

    申请人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

    发明人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

    IPC分类号： G06F9/315

    CPC分类号： G06F12/04 ,  G06F9/30025

    摘要： The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

    摘要翻译： 本发明提供了一种数据处理装置，其中可以共同使用程序，并且可以共享矢量表，而不管双端系统中的类型如何。 指令固定为小端，用于执行指令的数据的端序是可变的。 向量表中各向量地址的大小为32位，数据访问时的位数最多为32位。 CPU取指令，在执行取指令之前，CPU访问例如存储器中的32位数据。 此时，CPU控制对准器，使得要存储在数据寄存器中的字节单元中的每个地址中的数据的地址和对齐与由指令的小尾数确定的数据的地址和对齐相同，而不依赖于 数据的endian。

    METHOD OF GENERATING PROGRAM, INFORMATION PROCESSING DEVICE AND MICROCOMPUTER
    2.
    发明申请
    METHOD OF GENERATING PROGRAM, INFORMATION PROCESSING DEVICE AND MICROCOMPUTER 审中-公开
    产生程序，信息处理设备和微型计算机的方法

    公开(公告)号：US20080271001A1

    公开(公告)日：2008-10-30

    申请号：US11853058

    申请日：2007-09-11

    申请人： Yo Nonomura ,  Shunsuke Ota ,  Takashi Endo ,  Takashi Tsukamoto ,  Ichiro Kyushima ,  Hiromi Nagayama ,  Kenichi Hirane ,  Yoshiyuki Amanuma

    发明人： Yo Nonomura ,  Shunsuke Ota ,  Takashi Endo ,  Takashi Tsukamoto ,  Ichiro Kyushima ,  Hiromi Nagayama ,  Kenichi Hirane ,  Yoshiyuki Amanuma

    IPC分类号： G06F9/45

    CPC分类号： G06F21/77 ,  G06F8/41 ,  G06F21/125

    摘要： In programming in high-level language, a method of generating a program supporting external specifications for generating secure codes having high tamper-resistance and automatically generating an executable program having tamper-resistance with regard to a portion designated by a user is provided. A syntax analysis step, an intermediate representation generation step, a register allocation step, an optimization processing step, an assembly language generation step, a machine language generation step and a machine language program linkage step are executed. And between finish of reading of the source program and generating the executable program, a tamper-resistant code insertion step of automatically generating a code having tamper-resistance coping with unjust analysis of an operation content of the executable program is executed to the source program, the intermediate representation, the assembly language program or the machine language program based on an instruction of a user.

    摘要翻译： 在高级语言编程中，提供一种产生支持用于生成具有高抗篡改性的安全代码的外部规范的程序的方法，并且自动生成关于由用户指定的部分具有防篡改的可执行程序。 执行语法分析步骤，中间表示生成步骤，寄存器分配步骤，优化处理步骤，汇编语言生成步骤，机器语言生成步骤和机器语言程序链接步骤。 并且在源程序的读取完成和生成可执行程序之间，对源程序执行防篡改代码插入步骤，其自动产生具有防篡改的代码，并对不可执行程序的操作内容进行不正确的分析， 中间表示，汇编语言程序或基于用户的指令的机器语言程序。

    Single-chip microcomputer having an expandable address area
    5.
    发明授权
    Single-chip microcomputer having an expandable address area 失效
    具有可扩展地址区域的单片微计算机

    公开(公告)号：US5687344A

    公开(公告)日：1997-11-11

    申请号：US583763

    申请日：1996-01-10

    申请人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

    发明人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  G06F12/00 ,  G06F12/06 ,  G06F15/00 ,  G06F7/33

    CPC分类号： G06F9/30014 ,  G06F12/0623 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/321 ,  G06F9/324 ,  G06F9/342 ,  G06F9/35

    摘要： Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, by dividing it in half or by dividing it in quarters. As a result, the register can be used on software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

    摘要翻译： 扩展寄存器E0至E7被添加到内置于8位CPU（1）中的现有通用寄存器R0至R7中，以便将包含增加的扩展寄存器的所有寄存器全部作为访问地址数据 记忆体等。 地址操作在包括扩展寄存器和对应的通用寄存器的单元中执行。 包括扩展寄存器在内的所有寄存器被作为地址数据的一个单位来处理，以处理在地址操作中引起的进位或借位。 由于扩展寄存器的应用限于地址的生成，所以减少了可执行指令的种类或组合的数量，而不会严重降低数据处理能力，从而抑制CPU的逻辑和物理尺度的增加。 通过将16位的扩展寄存器Ei添加到8位CPU的16位的通用寄存器RiH和RiL，将寄存器整体提供32位。 该寄存器可以整体使用，通过将其分成两半或将其除以季度。 因此，该寄存器可用于软件或硬件，以减少CPU的逻辑和物理尺度。 此外，关于使用寄存器的地址数据的锁存全部或部分，可以容易地扩展要线性使用的地址空间。

    Data processing device having an expandable address space
    6.
    发明授权
    Data processing device having an expandable address space 失效
    具有可扩展地址空间的数据处理设备

    公开(公告)号：US5666510A

    公开(公告)日：1997-09-09

    申请号：US582379

    申请日：1996-01-11

    申请人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

    发明人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  G06F12/06 ,  G06F7/20

    CPC分类号： G06F9/30014 ,  G06F12/0623 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30192 ,  G06F9/342 ,  G06F9/35

    摘要： A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.

    摘要翻译： CPU与低位CPU具有较高的兼容性，可以相对扩展连续可用的地址空间。 为了锁定数据信息，寄存器被构造为具有位数大于低位CPU的地址位数的地址寄存器。 数据信息具有由操作码的大小位指定的字节/字长。 长字大小的数据信息的使用由新添加与低位CPU的相同位数的前缀码或操作码指定。 对于字节大小的数据信息，要使用的字节大小寄存器的高/低位由寄存器指定字段的预定1位指定。 对于字大小的数据信息，字大小寄存器的高/低位由该数据信息的预定1位指定。

    Saturated polyester bottle-shaped container with hard coating and method of fabricating the same
    7.
    发明授权
    Saturated polyester bottle-shaped container with hard coating and method of fabricating the same 失效
    具有硬涂层的饱和聚酯瓶形容器及其制造方法

    公开(公告)号：US4569869A

    公开(公告)日：1986-02-11

    申请号：US263509

    申请日：1981-05-14

    申请人： Hideo Kushida ,  Akikazu Kosugi ,  Hiromi Nagayama

    发明人： Hideo Kushida ,  Akikazu Kosugi ,  Hiromi Nagayama

    IPC分类号： B05D7/02 ,  B65D8/04 ,  B65D23/08 ,  C08J7/04

    CPC分类号： C08J7/04 ,  B05D7/02 ,  B65D23/08 ,  B65D23/0814 ,  B05D3/067 ,  C08J2367/02 ,  Y10T428/1352 ,  Y10T428/1383

    摘要： This invention relates to a saturated polyester bottle-shaped container and a method of fabricating the same from a material such as polyethylene terephthalate incorporating high transparency and superior mechanical surface strength. The hard coating is formed by the steps of coating an ultraviolet curable coating of methyl methacrylate resin on the surface of the body and irradiating ultraviolet rays over the surface of the body coated with the hard coating. Thus, the bottle-shaped container can largely enhance the wear resistance and extreme smoothness of the surface to eliminate dirt adherence onto the surface. In a second embodiment, an ultraviolet ray curable coating is coated onto the bottle, followed by a transparent resin coating which is cross linked with the ultraviolet ray curable coating.

    摘要翻译： 本发明涉及一种饱和聚酯瓶形容器及其制造方法，该材料由诸如聚对苯二甲酸乙二醇酯的材料制成，其具有高透明度和优异的机械表面强度。 通过以下步骤形成硬涂层：在身体表面涂覆甲基丙烯酸甲酯树脂的紫外线固化涂层，并在涂覆有硬涂层的主体表面上照射紫外线。 因此，瓶形容器可以大大增强表面的耐磨性和极端平滑度，以消除粘附在表面上的污垢。 在第二实施方案中，将紫外线固化涂料涂覆到瓶子上，然后与紫外线固化涂层交联的透明树脂涂层。

    Data processing device and semiconductor intergrated circuit device for a bi-endian system
    8.
    发明授权
    Data processing device and semiconductor intergrated circuit device for a bi-endian system 有权
    用于双端系统的数据处理设备和半导体集成电路器件

    公开(公告)号：US09524237B2

    公开(公告)日：2016-12-20

    申请号：US13063347

    申请日：2009-05-28

    申请人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

    发明人： Naoshi Ishikawa ,  Seiji Ikari ,  Hiromi Nagayama

    IPC分类号： G06F12/04 ,  G06F9/30

    CPC分类号： G06F12/04 ,  G06F9/30025

    摘要： The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a bi-endian system. An instruction is fixed to little endian, and endian of data to be used for executing the instruction is variable. A size of the respective vector addresses in the vector table is 32 bits, and the number of bits at the time of a data access is maximally 32 bits. A CPU fetches an instruction, and before the fetched instruction is executed, the CPU accesses to, for example, for 32-bit data in a memory. At this time, the CPU controls the aligner so that addresses and alignments of data to be stored in each address in byte unit in a data register are identical to addresses and alignments of data determined by little endian of an instruction without depending on types of the endian of the data.

    摘要翻译： 本发明提供了一种数据处理装置，其中可以共同使用程序，并且可以共享矢量表，而不管双端系统中的类型如何。 指令固定为小端，用于执行指令的数据的端序是可变的。 向量表中各向量地址的大小为32位，数据访问时的位数最多为32位。 CPU取指令，在执行取指令之前，CPU访问例如存储器中的32位数据。 此时，CPU控制对准器，使得要存储在数据寄存器中的字节单元中的每个地址中的数据的地址和对齐与由指令的小尾数确定的数据的地址和对齐相同，而不依赖于 数据的endian。

    Single-chip microcomputer having an expandable address area
    9.
    发明授权
    Single-chip microcomputer having an expandable address area 失效
    具有可扩展地址区域的单片微计算机

    公开(公告)号：US5771363A

    公开(公告)日：1998-06-23

    申请号：US607568

    申请日：1996-02-27

    申请人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

    发明人： Naoki Mitsuishi ,  Shiro Baba ,  Hiromi Nagayama ,  Tsutomu Hayashi ,  Yukihide Hayakawa

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355 ,  G06F12/00 ,  G06F12/06 ,  G06F15/00

    CPC分类号： G06F9/30014 ,  G06F12/0623 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/321 ,  G06F9/324 ,  G06F9/342 ,  G06F9/35

    摘要： Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in a CPU 1 of 8 bits so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU. This register can be used in its entirety, dividing it in half or by dividing it in quarters. As a result, the register can be excellently used on a software or hardware to reduce the logical and physical scales of the CPU. In respect of the latch of the address data using the register wholly or partially, moreover, the address space to be linearly used can be easily expanded.

    摘要翻译： 扩展寄存器E0至E7被添加到内置于8位的CPU 1中的现有的通用寄存器R0至R7中，使得包括所添加的扩展寄存器的所有寄存器可以作为访问存储器的地址数据全部被掌握 或类似物。 地址操作在包括扩展寄存器和对应的通用寄存器的单元中执行。 包括扩展寄存器在内的所有寄存器被作为地址数据的一个单位来处理，以处理在地址操作中引起的进位或借位。 由于扩展寄存器的应用限于地址的生成，所以减少了可执行指令的种类或组合的数量，而不会严重降低数据处理能力，从而抑制CPU的逻辑和物理尺度的增加。 通过将16位的扩展寄存器Ei添加到8位CPU的16位的通用寄存器RiH和RiL，将寄存器整体提供32位。 该寄存器可以全部使用，将其除以一半或将其除以季度。 因此，可以在软件或硬件上极大地使用寄存器，以减少CPU的逻辑和物理尺寸。 此外，关于使用寄存器的地址数据的锁存全部或部分，可以容易地扩展要线性使用的地址空间。