Invention Grant
- Patent Title: Obscuring memory access patterns in conjunction with deadlock detection or avoidance
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Application No.: US13782416Application Date: 2013-03-01
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Publication No.: US09524240B2Publication Date: 2016-12-20
- Inventor: Shay Gueron , Gad Sheaffer , Shlomo Raikin
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F12/14
- IPC: G06F12/14 ; G06F12/08 ; G06F21/55 ; H04L9/00

Abstract:
Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
Public/Granted literature
- US20130179643A1 OBSCURING MEMORY ACCESS PATTERNS IN CONJUNCTION WITH DEADLOCK DETECTION OR AVOIDANCE Public/Granted day:2013-07-11
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