Invention Grant
- Patent Title: Method for decomposing a layout of an integrated circuit
- Patent Title (中): 分解集成电路布局的方法
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Application No.: US14690491Application Date: 2015-04-20
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Publication No.: US09524361B2Publication Date: 2016-12-20
- Inventor: Ting-Cheng Tseng , Ming-Jui Chen , Chia-Wei Huang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.
Public/Granted literature
- US20160306910A1 METHOD FOR DECOMPOSING A LAYOUT OF AN INTEGRATED CIRCUIT Public/Granted day:2016-10-20
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