Invention Grant
- Patent Title: Lower page read for multi-level cell memory
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Application No.: US14954002Application Date: 2015-11-30
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Publication No.: US09524774B2Publication Date: 2016-12-20
- Inventor: Robert E. Frickey , Yogesh B. Wakchaure , Iwen Chao , Xin Guo , Kristopher H. Gaewsky
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C16/34 ; G06F12/02

Abstract:
An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.
Public/Granted literature
- US20160155497A1 LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY Public/Granted day:2016-06-02
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