发明授权
US09524955B2 Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure
有权
围绕垂直互连结构形成无流动底部填充材料的半导体器件和方法
- 专利标题： Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure
- 专利标题（中）： 围绕垂直互连结构形成无流动底部填充材料的半导体器件和方法
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申请号： US13423782申请日： 2012-03-19
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公开(公告)号： US09524955B2公开(公告)日： 2016-12-20
- 发明人: Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow
- 申请人： Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow
- 申请人地址： SG Singapore
- 专利权人： STATS ChipPAC Pte. Ltd.
- 当前专利权人： STATS ChipPAC Pte. Ltd.
- 当前专利权人地址： SG Singapore
- 代理机构： Patent Law Group: Atkins and Associates, P.C.
- 代理商 Robert D. Atkins
- 主分类号： H01L23/02
- IPC分类号： H01L23/02 ; H01L25/10 ; H01L21/56 ; H01L23/31 ; H01L25/065 ; H01L25/03 ; H01L23/00
摘要：
A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
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