Invention Grant
- Patent Title: Limiting aging effects in analog differential circuits
- Patent Title (中): 限制模拟差分电路中的老化效应
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Application No.: US15042675Application Date: 2016-02-12
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Publication No.: US09531398B2Publication Date: 2016-12-27
- Inventor: Paul F. Ferguson , Gabriele Manganaro
- Applicant: ANALOG DEVICES. INC.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Patent Capital Group
- Main IPC: H03M1/06
- IPC: H03M1/06 ; G01R31/28 ; H03M1/12

Abstract:
Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.
Public/Granted literature
- US20160269038A1 LIMITING AGING EFFECTS IN ANALOG DIFFERENTIAL CIRCUITS Public/Granted day:2016-09-15
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