公开(公告)号：US09531398B2

公开(公告)日：2016-12-27

申请号：US15042675

申请日：2016-02-12

Applicant: ANALOG DEVICES. INC.

Inventor： Paul F. Ferguson ,  Gabriele Manganaro

IPC: H03M1/06 ,  G01R31/28 ,  H03M1/12

CPC classification number: H03M1/06 ,  G01R31/2642 ,  G01R31/2872 ,  H03M1/12

Abstract: Aging effects on devices fabricated using deep nanometer complementary metal-oxide semiconductor (CMOS) processes can cause circuits to exhibit an undesirable mismatch buildup over time. To address the aging effects, the connections to an array of M differential circuits are controlled to limit and systematically minimize or reverse the aging effects. In one embodiment, the controlling permutation sequence is selected to stress the array of M differential circuits under opposite stress conditions during at least two different time periods. Imposing opposite stress conditions, preferably substantially equal opposite stress conditions, can reverse the direction of a mismatch buildup and limit the mismatch buildup over time within acceptable limits. The controlling permutation sequence can be applied to an array of comparators of an analog-to-digital converter, or an array of differential amplifiers of a folding analog-to-digital converter.

Abstract translation: 使用深纳米互补金属氧化物半导体（CMOS）工艺制造的器件的老化效应可能导致电路随时间呈现出不期望的不匹配积累。 为了解决老化的影响，控制到一组M个差分电路的连接，以限制和系统地最小化或逆转老化效应。 在一个实施例中，选择控制置换序列以在至少两个不同时间段期间在相反的应力条件下对M个差分电路的阵列施加应力。 施加相反的应力条件，优选地基本上相等的相对应力条件可以反转不匹配积累的方向，并且在可接受的限度内限制不匹配的积累。 控制置换序列可以应用于模数转换器的比较器阵列，或折叠模数转换器的差分放大器阵列。