Invention Grant
- Patent Title: Margin test methods and circuits
- Patent Title (中): 保证金测试方法和电路
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Application No.: US14817607Application Date: 2015-08-04
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Publication No.: US09544071B2Publication Date: 2017-01-10
- Inventor: Andrew Ho , Vladimir Stojanovic , Bruno W. Garlepp , Fred F. Chen
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Silicon Edge Law Group LLP
- Agent Arthur J. Behiel
- Main IPC: H04B17/29
- IPC: H04B17/29 ; H04L27/01 ; H04L25/03 ; G01R31/317 ; H04L1/20 ; H04L1/24 ; H04L7/033 ; G06F11/08 ; H04B17/21 ; H04L7/04 ; H04L7/10

Abstract:
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
Public/Granted literature
- US20150341128A1 Margin Test Methods and Circuits Public/Granted day:2015-11-26
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