Invention Grant
US09544231B2 Packet processing VLIW action unit with OR-multi-ported instruction memory
有权
分组处理VLIW动作单元，带有或多端口指令存储器
- Patent Title: Packet processing VLIW action unit with OR-multi-ported instruction memory
- Patent Title (中): 分组处理VLIW动作单元，带有或多端口指令存储器
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Application No.: US15017770Application Date: 2016-02-08
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Publication No.: US09544231B2Publication Date: 2017-01-10
- Inventor: Patrick William Bosshart , Hun-Seok Kim
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/56 ; H04L12/741 ; H04L12/935 ; H04L12/743
Abstract:
An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.
Public/Granted literature
- US20160156557A1 Packet Processing VLIW Action Unit with Or-Multi-Ported Instruction Memory Public/Granted day:2016-06-02
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