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公开(公告)号：US09646105B2
公开(公告)日：2017-05-09
申请号：US13922327
申请日：2013-06-20
发明人： Hun-Seok Kim , Patrick Bosshart
IPC分类号： G06F17/30 , G06F12/1018 , G06F12/0864
CPC分类号： G06F17/30949 , G06F12/0864 , G06F12/1018
摘要： Hashing complexity is reduced by exploiting a hashing matrix structure that permits a corresponding hashing function to be implemented such that an output vector of bits is produced in response to an input vector of bits without combining every bit in the input vector with every bit in any row of the hashing matrix.
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2.发明授权Packet processing VLIW action unit with OR-multi-ported instruction memory 有权分组处理VLIW动作单元，带有或多端口指令存储器公开(公告)号：US09544231B2
公开(公告)日：2017-01-10
申请号：US15017770
申请日：2016-02-08
IPC分类号： H04L12/28 , H04L12/56 , H04L12/741 , H04L12/935 , H04L12/743
CPC分类号： H04L45/745 , H04L45/74 , H04L45/7457 , H04L49/3063
摘要： An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.
摘要翻译： 本发明的实施例包括用于交换网络中的分组处理的存储器和装置。 存储器包括多个单词，其中每个单词包括多个位。 多个单词中的每个单词通过单独和不同的读取地址来寻址。 逻辑电路对由单独和不同读取地址寻址的所有单词中的所有位执行逻辑“或”功能，并输出结果。
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公开(公告)号：US20140334489A1
公开(公告)日：2014-11-13
申请号：US14072989
申请日：2013-11-06
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/875 , H04L12/741
CPC分类号： H04L47/56 , H04L45/24 , H04L45/745 , H04L69/22
摘要： An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.
摘要翻译： 本发明的实施例包括分组处理流水线。 分组处理流水线包括匹配和动作阶段。 当匹配处理发生时，每个匹配和动作阶段引起匹配延迟，并且当发生动作处理时，每个匹配和动作阶段引起动作延迟。 当数据从第一个匹配和动作阶段转移到第二个匹配和动作阶段时，在连续匹配和动作阶段之间发生传输延迟。
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公开(公告)号：US20140241358A1
公开(公告)日：2014-08-28
申请号：US14190734
申请日：2014-02-26
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/743
CPC分类号： H04L45/7453 , G06F9/3853 , H04L45/7457
摘要： An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.
摘要翻译： 本发明的实施例包括接收分组报头向量，其中报头向量包括多个分组报头字。 对分组头文字执行匹配操作。 基于匹配操作来修改至少一个分组报头字。 对于每个分组报头字使用至少一个处理器来执行分组匹配操作并修改至少一个分组报头字。 从VLIW指令字包括所有指令字的指令字接收指令。 每个处理器响应于指令字执行操作。
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公开(公告)号：US20170289034A1
公开(公告)日：2017-10-05
申请号：US15622936
申请日：2017-06-14
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/741
CPC分类号： H04L45/74
摘要： A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.
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公开(公告)号：US09712439B2
公开(公告)日：2017-07-18
申请号：US14193177
申请日：2014-02-28
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/741
CPC分类号： H04L45/74
摘要： A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.
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7.发明申请公开(公告)号：US20140241361A1
公开(公告)日：2014-08-28
申请号：US14193177
申请日：2014-02-28
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/743
CPC分类号： H04L45/74
摘要： A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.
摘要翻译： 一个数据包处理块。 该块包括用于在分组报头向量中接收数据的输入，该矢量包括表示分组信息的数据值。 该块还包括用于响应于分组报头向量和存储在匹配表中的数据的至少一部分来执行分组匹配操作的电路，以及用于响应于由用于执行分组的电路检测到的匹配而执行一个或多个动作的电路 匹配操作和根据存储在操作表中的信息。 所述匹配表和所述动作表中的每一个包括从单元存储器池中选择的一个或多个存储器，其中单元存储器池中的每个存储器可配置为作为匹配存储器或动作存储器操作。
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公开(公告)号：US09998574B2
公开(公告)日：2018-06-12
申请号：US15788179
申请日：2017-10-19
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/701 , H04L29/06 , H04L12/741
摘要： A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.
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公开(公告)号：US09826067B2
公开(公告)日：2017-11-21
申请号：US14193190
申请日：2014-02-28
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/701 , H04L29/06 , H04L12/741
摘要： A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.
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10.发明申请公开(公告)号：US20140241359A1
公开(公告)日：2014-08-28
申请号：US14190770
申请日：2014-02-26
发明人： Patrick W. Bosshart , Hun-Seok Kim
IPC分类号： H04L12/741
CPC分类号： H04L45/745 , H04L45/74 , H04L45/7457 , H04L49/3063
摘要： An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.
摘要翻译： 本发明的实施例包括用于交换网络中的分组处理的存储器和装置。 存储器包括多个单词，其中每个单词包括多个位。 多个单词中的每个单词通过单独和不同的读取地址来寻址。 逻辑电路对由单独和不同读取地址寻址的所有单词中的所有位执行逻辑“或”功能，并输出结果。
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