Invention Grant
- Patent Title: Clock tree circuit and memory controller
- Patent Title (中): 时钟树电路和内存控制器
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Application No.: US14980362Application Date: 2015-12-28
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Publication No.: US09557764B2Publication Date: 2017-01-31
- Inventor: Chen-Feng Chiang , Kai-Hsin Chen , Ming-Shi Liou , Chih-Tsung Yao
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G06F1/10 ; G11C11/4076 ; G11C11/4094 ; G06F13/16 ; G11C7/22 ; G11C7/10

Abstract:
A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.
Public/Granted literature
- US20160132071A1 CLOCK TREE CIRCUIT AND MEMORY CONTROLLER Public/Granted day:2016-05-12
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