Invention Grant
US09557764B2 Clock tree circuit and memory controller 有权
时钟树电路和内存控制器

Clock tree circuit and memory controller
Abstract:
A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.
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