公开(公告)号：US10083728B2

公开(公告)日：2018-09-25

申请号：US14324228

申请日：2014-07-06

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

IPC: G06F12/00 ,  G11C8/12 ,  G06F13/16

CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

公开(公告)号：US20150074346A1

公开(公告)日：2015-03-12

申请号：US14324228

申请日：2014-07-06

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

IPC: G11C7/10 ,  G11C8/12

CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

Abstract translation: 一种存储器模块，包括：第一引脚，布置成接收第一信号; 布置成接收第二信号的第二引脚; 第一导电路径，其具有耦合到第一引脚的第一端; 至少一个存储器芯片，耦合到所述第一导电路径，用于接收所述第一信号; 预定的电阻器，具有耦合到第一导电路径的第二端的第一端子; 以及第二导电路径，其具有耦合到第二引脚的第一端，用于将第二端子传导到预定电阻器的第二端子; 其中所述第一信号和所述第二信号是同步的并且被配置为差分信号，用于使来自所述至少一个存储器芯片的所选择的存储器芯片被访问。

公开(公告)号：US20140321473A1

公开(公告)日：2014-10-30

申请号：US14230005

申请日：2014-03-31

Applicant: MEDIATEK INC.

Inventor： Yu-Hsun Chen ,  Yi-Hsin Yu ,  Ming-Shi Liou ,  Ming Zhang

IPC: H04L12/861

CPC classification number: H04L49/90 ,  H04L47/39

Abstract: An active output buffer controller is used for controlling a packet data output of a main buffer in a network device. The active output buffer controller has a credit evaluation circuit and a control logic. The credit evaluation circuit estimates a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device. The control logic compares the credit value with a first predetermined threshold value to generate a comparison result, and controls the packet data output of the main buffer according to at least the comparison result.

Abstract translation: 主动输出缓冲控制器用于控制网络设备中主缓冲区的分组数据输出。 有源输出缓冲器控制器具有信用评估电路和控制逻辑。 信用评估电路基于网络设备的入口数据接收状态和网络设备的出口数据传输状态中的至少一个来估计信用值。 控制逻辑将信用值与第一预定阈值进行比较以产生比较结果，并且至少根据比较结果来控制主缓冲器的分组数据输出。

公开(公告)号：US09557764B2

公开(公告)日：2017-01-31

申请号：US14980362

申请日：2015-12-28

Applicant: MediaTek Inc.

Inventor： Chen-Feng Chiang ,  Kai-Hsin Chen ,  Ming-Shi Liou ,  Chih-Tsung Yao

IPC: G11C7/00 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/4094 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F1/10 ,  G06F13/16 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4094

Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.

Abstract translation: 时钟树电路包括第一时钟源，产生第一信号和第一树电路。 第一时钟树电路包括用于接收第一信号的第一驱动级，连接到第一驱动级的第二驱动级，连接到第二驱动级的第三驱动级和耦合在不同节点之间的金属连接元件 并配置为短路元件。

公开(公告)号：US09256245B2

公开(公告)日：2016-02-09

申请号：US14602562

申请日：2015-01-22

Applicant: MediaTek Inc.

Inventor： Chen-Feng Chiang ,  Kai-Hsin Chen ,  Ming-Shi Liou ,  Chih-Tsung Yao

IPC: G11C7/00 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G06F1/10 ,  G06F13/16 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4094

Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.

Abstract translation: 时钟树电路包括时钟源和树电路。 时钟源产生一个信号。 树电路至少包括五个驱动单元和金属连接元件。 第一驱动单元具有用于接收信号的输入端子和耦合到第一节点的输出端子。 第二驱动单元具有耦合到第一节点的输入端子和耦合到第二节点的输出端子。 第三驱动单元具有耦合到第一节点的输入端子和耦合到第三节点的输出端子。 第四驱动单元具有耦合到第二节点的输入端子。 第五驱动单元具有耦合到第三节点的输入端。 金属连接元件耦合在第二节点和第三节点之间，并被配置为短路元件。