发明授权
US09558998B2 Systems and methods for producing flat surfaces in interconnect structures
有权
用于在互连结构中产生平坦表面的系统和方法
- 专利标题: Systems and methods for producing flat surfaces in interconnect structures
- 专利标题(中): 用于在互连结构中产生平坦表面的系统和方法
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申请号: US15066238申请日: 2016-03-10
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公开(公告)号: US09558998B2公开(公告)日: 2017-01-31
- 发明人: Cyprian Uzoh , Vage Oganesian , Ilyas Mohammed
- 申请人: Tessera, Inc.
- 申请人地址: US CA San Jose
- 专利权人: Tessera, Inc.
- 当前专利权人: Tessera, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Haynes and Boone, LLP
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763 ; H01L21/768 ; H01L21/321 ; H01L23/48
摘要:
In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.
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