An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit includes a first input node configured to receive a first input voltage, a second input node configured to receive a second input voltage, a first output node configured to provide a first output voltage, and a second output node configured to provide a second output voltage. The first circuitry is configured to accelerate a voltage level transition of the first output voltage at the first output node responsive to the first input voltage at the first input node. The second circuitry is configured to accelerate a voltage level transition of the second output voltage at the second output node responsive to the second input voltage at the second input node.