公开(公告)号：US09570158B1

公开(公告)日：2017-02-14

申请号：US15146070

申请日：2016-05-04

Applicant: QUALCOMM Incorporated

Inventor： Priyankar Mathuria ,  Gururaj Shamanna ,  VRC Krishna Teja Kunisetty

IPC: G11C7/10 ,  G11C11/419 ,  H03K3/356 ,  H03K3/037

CPC classification number: G11C11/419 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/356104

Abstract: An integrated circuit (IC) is disclosed herein for accelerating memory access with an output latch. In an example aspect, the output latch includes a data storage unit, first circuitry, and second circuitry. The data storage unit includes a first input node configured to receive a first input voltage, a second input node configured to receive a second input voltage, a first output node configured to provide a first output voltage, and a second output node configured to provide a second output voltage. The first circuitry is configured to accelerate a voltage level transition of the first output voltage at the first output node responsive to the first input voltage at the first input node. The second circuitry is configured to accelerate a voltage level transition of the second output voltage at the second output node responsive to the second input voltage at the second input node.

Abstract translation: 本文公开了一种用于利用输出锁存器加速存储器存取的集成电路（IC）。 在示例方面，输出锁存器包括数据存储单元，第一电路和第二电路。 数据存储单元包括被配置为接收第一输入电压的第一输入节点，被配置为接收第二输入电压的第二输入节点，被配置为提供第一输出电压的第一输出节点和被配置为提供第一输出节点的第二输出节点 第二输出电压。 第一电路被配置为响应于第一输入节点处的第一输入电压来加速第一输出节点处的第一输出电压的电压电平转变。 第二电路被配置为响应于第二输入节点处的第二输入电压而加速第二输出节点处的第二输出电压的电压电平转变。