Invention Grant
- Patent Title: Trap rich layer for semiconductor devices
- Patent Title (中): 陷阱丰富的半导体器件层
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Application No.: US14855652Application Date: 2015-09-16
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Publication No.: US09570558B2Publication Date: 2017-02-14
- Inventor: Christopher N. Brindle , Michael A. Stuber , Stuart B. Molin
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L29/10 ; H01L21/84 ; H01L27/12 ; H01L29/78 ; H01L21/20 ; H01L21/02 ; H01L21/265 ; H01L21/306 ; H01L21/768 ; H01L23/00 ; H01L23/528 ; H01L25/065 ; H01L25/00
Abstract:
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
Public/Granted literature
- US20160035833A1 TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES Public/Granted day:2016-02-04
Information query
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