公开(公告)号：US09881881B2

公开(公告)日：2018-01-30

申请号：US14809141

申请日：2015-07-24

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher N. Brindle ,  Anton Arriagada

IPC: H01L23/522 ,  H01L23/52 ,  H01L23/58 ,  H01L23/66 ,  H01L23/60 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/562 ,  H01L23/60 ,  H01L23/66

Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.

公开(公告)号：US09570558B2

公开(公告)日：2017-02-14

申请号：US14855652

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Christopher N. Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Abstract translation: 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。

公开(公告)号：US20170025368A1

公开(公告)日：2017-01-26

申请号：US14809141

申请日：2015-07-24

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher N. Brindle ,  Anton Arriagada

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/66 ,  H01L23/60 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/585 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/562 ,  H01L23/60 ,  H01L23/66

Abstract: A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.

Abstract translation: 多块半导体器件包括彼此以不同功率方式工作的第一块和第二块。 密封环围绕模具的周边，密封第一和第二块。 模具具有基板和绝缘层，密封环位于绝缘层上。 密封圈用作第一块的电源总线，但不是第二个块。 密封环和第一块电耦合到第一接地节点，第一接地节点与多块半导体器件中的其它接地节点在晶片级电隔离。 在一些实施例中，第二块位于模具的中心区域中，并且多个金属线将密封环电连接到第一块，金属线围绕半导体管芯的大部分周边均匀间隔开。