公开(公告)号：US20190386026A1

公开(公告)日：2019-12-19

申请号：US16553362

申请日：2019-08-28

Applicant: QUALCOMM INCORPORATED

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L21/683

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US09570558B2

公开(公告)日：2017-02-14

申请号：US14855652

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Christopher N. Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Abstract translation: 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。

公开(公告)号：US20170243887A1

公开(公告)日：2017-08-24

申请号：US15588945

申请日：2017-05-08

Applicant: QUALCOMM INCORPORATED

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/082 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US20160359002A1

公开(公告)日：2016-12-08

申请号：US15241359

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber ,  Max Aubain

IPC: H01L29/10 ,  H01L23/367 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78654 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03845 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract translation: 本发明的实施例提供了使用应变层的半导体结构中的晶体管的增强。 该结构包括由挖掘区域和图案区域构成的图案层，位于挖掘区域和图案区域上的应变层，位于应变层上方的有源层，形成在有源层中的场效应晶体管，以及 位于有源层上方的手柄层。 场效应晶体管包括源极，漏极和沟道。 通道完全位于图案区域的横向范围内。 源极和漏极各自仅部分地位于图案区域的横向范围内。 应变层改变通道的载流子迁移率。 在一些实施例中，将应变层引入到绝缘体上半导体结构的背面。

公开(公告)号：US09466536B2

公开(公告)日：2016-10-11

申请号：US14451342

申请日：2014-08-04

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Stuart B. Molin ,  George P. Imthurn

IPC: H01L21/30 ,  H01L21/00 ,  H01L21/46 ,  H01L21/84 ,  H01L21/762 ,  H01L21/3213 ,  H01L23/48 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76256 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for manufacturing semiconductor-on-insulator (SOI) integrated circuits are disclosed. An SOI wafer is provided having a first surface and a second surface. The substrate of the SOI wafer forms the second surface. A transistor is formed in the semiconductor layer of the SOI wafer. A handle wafer is bonded to the first surface of the SOI wafer. The substrate layer is then removed to expose a back surface of the buried insulator of the SOI wafer. Conductive material is deposited on the SOI wafer that covers the back surface of the buried insulator. The conductive material is patterned to form a second gate electrode for the transistor on the back surface of the insulator.

Abstract translation: 公开了制造绝缘体上半导体（SOI）集成电路的方法。 提供具有第一表面和第二表面的SOI晶片。 SOI晶片的衬底形成第二表面。 晶体管形成在SOI晶片的半导体层中。 把手晶片结合到SOI晶片的第一表面。 然后去除衬底层以暴露SOI晶片的埋入绝缘体的背表面。 导电材料沉积在覆盖掩埋绝缘体背面的SOI晶片上。 将导电材料图案化以形成用于绝缘体背面上的晶体管的第二栅电极。

公开(公告)号：US10431598B2

公开(公告)日：2019-10-01

申请号：US15588945

申请日：2017-05-08

Applicant: QUALCOMM INCORPORATED

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/732 ,  H01L21/8234 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78 ,  H01L21/683 ,  H01L29/417 ,  H01L21/84 ,  H01L29/73 ,  H01L23/00 ,  H01L23/48

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US09515139B2

公开(公告)日：2016-12-06

申请号：US14746398

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Anton Arriagada ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30 ,  H01L29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L21/268 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L29/0692 ,  H01L21/02365 ,  H01L21/2007 ,  H01L21/268 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/84 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

公开(公告)号：US10079230B2

公开(公告)日：2018-09-18

申请号：US15240009

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  Stuart B. Molin

IPC: H01L29/66 ,  H01L27/082 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/088 ,  H01L29/06 ,  H01L21/683 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC classification number: H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

公开(公告)号：US09754860B2

公开(公告)日：2017-09-05

申请号：US14326304

申请日：2014-07-08

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Michael A. Stuber ,  Mark Drucker

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L21/322 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/2007 ,  H01L21/3221 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/13

Abstract: A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.

公开(公告)号：US09673219B2

公开(公告)日：2017-06-06

申请号：US14576122

申请日：2014-12-18

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78 ,  H01L21/683 ,  H01L21/84 ,  H01L29/73 ,  H01L23/00 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.