Invention Grant
US09583574B2 Epitaxial buffer layers for group III-N transistors on silicon substrates
有权
在硅衬底上的III-N晶体管的外延缓冲层
- Patent Title: Epitaxial buffer layers for group III-N transistors on silicon substrates
- Patent Title (中): 在硅衬底上的III-N晶体管的外延缓冲层
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Application No.: US13631514Application Date: 2012-09-28
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Publication No.: US09583574B2Publication Date: 2017-02-28
- Inventor: Sansaptak Dasgupta , Han Wui Then , Niloy Mukherjee , Marko Radosavljevic , Robert S. Chau
- Applicant: Sansaptak Dasgupta , Han Wui Then , Niloy Mukherjee , Marko Radosavljevic , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/20
- IPC: H01L29/20 ; H01L29/205 ; H01L29/66 ; H01L29/778 ; H01L29/423

Abstract:
Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.
Public/Granted literature
- US20140094223A1 EPITAXIAL BUFFER LAYERS FOR GROUP III-N TRANSISTORS ON SILICON SUBSTRATES Public/Granted day:2014-04-03
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