公开(公告)号：US09634007B2

公开(公告)日：2017-04-25

申请号：US14302350

申请日：2014-06-11

申请人： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238

CPC分类号： H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

公开(公告)号：US08765563B2

公开(公告)日：2014-07-01

申请号：US13630527

申请日：2012-09-28

申请人： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Seung Hoon Sung ,  Niti Goel ,  Jack T. Kavalieros ,  Sansaptak Dasgupta ,  Van H. Le ,  Willy Rachmady ,  Marko Radosavljevic ,  Gilbert Dewey ,  Han Wui Then ,  Niloy Mukherjee ,  Matthew V. Metz ,  Robert S. Chau

IPC分类号： H01L21/00 ,  H01L21/311 ,  H01L21/8222 ,  H01L21/30 ,  H01L21/20 ,  H01L29/15

CPC分类号： H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

摘要翻译： 沟槽限制的选择性外延生长工艺，其中半导体器件层的外延生长在沟槽的范围内进行。 在实施例中，制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。 接种表面周围的半导体区域可以相对于接种表面凹陷，其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。 在形成沟槽的实施例中，牺牲性硬掩模翅片可以被覆盖在电介质中，然后将其平坦化以暴露硬掩模翅片，然后将其去除以暴露接种表面。 通过选择性异质外延从种子表面形成半导体器件层。 在实施例中，通过使隔离电介质的顶表面凹陷，从半导体器件层形成非平面器件。 在实施例中，可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。

公开(公告)号：US09099490B2

公开(公告)日：2015-08-04

申请号：US13631534

申请日：2012-09-28

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20

CPC分类号： H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

摘要翻译： 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US09583574B2

公开(公告)日：2017-02-28

申请号：US13631514

申请日：2012-09-28

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

IPC分类号： H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423

CPC分类号： H01L29/7787 ,  H01L23/535 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66545

摘要： Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.

摘要翻译： 实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。 在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。 这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。 使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

公开(公告)号：US20140158976A1

公开(公告)日：2014-06-12

申请号：US13706473

申请日：2012-12-06

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Robert S. Chau

IPC分类号： H01L21/36 ,  H01L29/06

CPC分类号： H01L29/0684 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  Y10S977/762

摘要： III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer.

摘要翻译： 公开了III-N半导体硅集成电路结构和技术。 在一些情况下，该结构包括在成核层上形成的第一半导体层，第一半导体层在成核层上包含3-D GaN层并具有多个3-D半导体结构，以及2-D ​​GaN层 在3-D GaN层上。 该结构还可以包括形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括二维GaN层上的AlGaN和AlGaN层上的GaN层。 另一种结构包括形成在成核层上的第一半导体层，第一半导体层包括成核层上的2-D GaN层，以及形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括AlGaN 在2-D GaN层和AlGaN层上的GaN层。

公开(公告)号：US10050015B2

公开(公告)日：2018-08-14

申请号：US15121759

申请日：2014-03-27

申请人： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Brian S. Doyle ,  Marko Radosavljevic ,  Han Wui Then

发明人： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Brian S. Doyle ,  Marko Radosavljevic ,  Han Wui Then

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L25/065 ,  H01L25/00 ,  H01L29/20 ,  H01L29/24 ,  G06F1/16 ,  G09F9/30 ,  G09G3/36 ,  H01L21/8258 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/822 ,  H01L27/06

摘要： Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

公开(公告)号：US08987091B2

公开(公告)日：2015-03-24

申请号：US13976840

申请日：2011-12-23

申请人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/336 ,  H01L31/00 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：US20140084239A1

公开(公告)日：2014-03-27

申请号：US13629148

申请日：2012-09-27

申请人： Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Dipanjan Basu ,  Sanaz K. Gardner ,  Satyarth Suri ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Han Wui Then ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Dipanjan Basu ,  Sanaz K. Gardner ,  Satyarth Suri ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Han Wui Then ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/267 ,  H01L29/06

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/201 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.

摘要翻译： 描述具有低带隙包层的沟道区的非平面半导体器件。 例如，半导体器件包括布置在衬底上方的多个纳米线的垂直布置。 每个纳米线包括具有第一带隙的内部区域和围绕内部区域的外部包层。 包层具有第二较低带隙。 栅堆叠设置在每个纳米线的沟道区上并完全包围。 栅极堆叠包括设置在包层上并围绕着包层的栅极电介质层和设置在栅极介电层上的栅电极。 源区和漏区设置在纳米线的沟道区的两侧。

公开(公告)号：US08785909B2

公开(公告)日：2014-07-22

申请号：US13629148

申请日：2012-09-27

申请人： Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Dipanjan Basu ,  Sanaz K. Gardner ,  Satyarth Suri ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Han Wui Then ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Dipanjan Basu ,  Sanaz K. Gardner ,  Satyarth Suri ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Han Wui Then ,  Robert S. Chau

IPC分类号： H01L29/06 ,  B82Y10/00 ,  H01L29/78

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/201 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.

摘要翻译： 描述具有低带隙包层的沟道区的非平面半导体器件。 例如，半导体器件包括布置在衬底上方的多个纳米线的垂直布置。 每个纳米线包括具有第一带隙的内部区域和围绕内部区域的外部包层。 包层具有第二较低带隙。 栅堆叠设置在每个纳米线的沟道区上并完全包围。 栅极堆叠包括设置在包层上并围绕着包层的栅极电介质层和设置在栅极介电层上的栅电极。 源区和漏区设置在纳米线的沟道区的两侧。

公开(公告)号：US20130292698A1

公开(公告)日：2013-11-07

申请号：US13976840

申请日：2011-12-23

申请人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/423 ,  H01L29/40

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.