Invention Grant
US09584432B2 Circular time differencing add/subtract delta to TMAX on sign, MSB
有权
循环时间差异加号/减法增量到TMAX符号，MSB
- Patent Title: Circular time differencing add/subtract delta to TMAX on sign, MSB
- Patent Title (中): 循环时间差异加号/减法增量到TMAX符号，MSB
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Application No.: US14812398Application Date: 2015-07-29
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Publication No.: US09584432B2Publication Date: 2017-02-28
- Inventor: Andrew W. Welin
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/08
- IPC: G01R31/08 ; G06F11/00 ; G08C15/00 ; H04J1/16 ; H04J3/14 ; H04L1/00 ; H04L12/863 ; H04L12/875 ; H04L12/841 ; G10L25/78 ; H04L12/54 ; H04L29/06 ; H04L12/801 ; H04L12/851 ; H04L12/853 ; H04L12/823 ; H04M1/253 ; H04L12/64
Abstract:
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
Public/Granted literature
- US20150341281A1 SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR IMPROVED PACKET SCHEDULING OF MEDIA OVER PACKET Public/Granted day:2015-11-26
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