Invention Grant
- Patent Title: Method for integrated circuit patterning
- Patent Title (中): 集成电路图案化方法
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Application No.: US14846112Application Date: 2015-09-04
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Publication No.: US09589800B2Publication Date: 2017-03-07
- Inventor: Szu-Ping Tung , Ching-Hua Hsieh , Huang-Yi Huang , Neng-Jye Yang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/302 ; H01L21/033 ; C23G1/02 ; H01L21/308 ; H01L21/3213
Abstract:
A method of forming a target pattern includes forming a plurality of lines over a substrate and forming spacer features on sidewalls of the lines. The method further includes shrinking the spacer features using a wet process. After the shrinking of the spacer features, the method further includes removing the lines thereby providing the shrunk spacer features over the substrate.
Public/Granted literature
- US20160071730A1 Method for Integrated Circuit Patterning Public/Granted day:2016-03-10
Information query
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