Invention Grant
- Patent Title: Alignment monitoring structure and alignment monitoring method for semiconductor devices
- Patent Title (中): 半导体器件的对准监测结构和对准监测方法
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Application No.: US14709889Application Date: 2015-05-12
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Publication No.: US09589854B2Publication Date: 2017-03-07
- Inventor: Dominik Olligs
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/66 ; H01L27/02 ; H01L27/088 ; H01L23/535 ; H01J37/28 ; G01B15/00 ; H01L23/544 ; H01L27/112

Abstract:
The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.
Public/Granted literature
- US20160336240A1 ALIGNMENT MONITORING STRUCTURE AND ALIGNMENT MONITORING METHOD FOR SEMICONDUCTOR DEVICES Public/Granted day:2016-11-17
Information query
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