公开(公告)号：US09589854B2

公开(公告)日：2017-03-07

申请号：US14709889

申请日：2015-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominik Olligs

IPC: H01L21/70 ,  H01L21/66 ,  H01L27/02 ,  H01L27/088 ,  H01L23/535 ,  H01J37/28 ,  G01B15/00 ,  H01L23/544 ,  H01L27/112

CPC classification number: H01L22/12 ,  G01B15/00 ,  H01J37/28 ,  H01L22/30 ,  H01L23/535 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/112 ,  H01L2223/54453

Abstract: The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.

Abstract translation: 本公开在各种方面提供了一种对准监视结构和方法，用于监测半导体器件（例如CMOS）中目标栅极导体与对应目标触点之间的对准。 根据这里的一些说明性实施例，提供了一种结构，其具有布置在衬底上的多个栅极导体，以便限定一排平行栅极导体和多个第一触点，其中每个第一触点设置在两个相邻的 栅极导体，以便限定第一栅极导体和第一触点之间的第一横向距离，以及第一触点和第二栅极导体之间​​的第二横向距离，并且其中第一横向距离和第二横向距离沿着该行系统地变化 的并联栅极导体。

公开(公告)号：US20160336240A1

公开(公告)日：2016-11-17

申请号：US14709889

申请日：2015-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominik Olligs

IPC: H01L21/66 ,  G01B15/00 ,  H01L23/535 ,  H01J37/28 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L22/12 ,  G01B15/00 ,  H01J37/28 ,  H01L22/30 ,  H01L23/535 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/112 ,  H01L2223/54453

Abstract: The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.

Abstract translation: 本公开在各种方面提供了一种对准监视结构和方法，用于监测半导体器件（例如CMOS）中目标栅极导体与对应目标触点之间的对准。 根据这里的一些说明性实施例，提供了一种结构，其具有布置在衬底上的多个栅极导体，以便限定一排平行栅极导体和多个第一触点，其中每个第一触点设置在两个相邻的 栅极导体，以便限定第一栅极导体和第一触点之间的第一横向距离，以及第一触点和第二栅极导体之间​​的第二横向距离，并且其中第一横向距离和第二横向距离沿着该行系统地变化 的并联栅极导体。

公开(公告)号：US09196684B2

公开(公告)日：2015-11-24

申请号：US14254710

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Frohberg ,  Peter Moll ,  Dominik Olligs ,  Heike Scholz

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7843

Abstract: A method of reducing the impact of FEoL topography on dual stress liner depositions and the resulting device are disclosed. Embodiments include forming a first nitride layer between and over a pFET and an nFET; thinning the first nitride layer; forming a second nitride layer over the first nitride layer; and removing the first and the second nitride layers from over the pFET.

Abstract translation: 公开了一种减少FEoL地形对双应力衬垫沉积物的影响的方法和所得到的装置。 实施例包括在pFET和nFET之间和之上形成第一氮化物层; 使第一氮化物层变薄; 在所述第一氮化物层上形成第二氮化物层; 以及从pFET上方去除第一和第二氮化物层。