Invention Grant
- Patent Title: Efficient buried oxide layer interconnect scheme
- Patent Title (中): 高效埋地氧化层互连方案
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Application No.: US15172536Application Date: 2016-06-03
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Publication No.: US09589983B2Publication Date: 2017-03-07
- Inventor: Russell Carlton McMullan
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jaqueline J. Garner; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L27/12 ; H01L23/48 ; H01L23/528 ; H01L23/522 ; H01L23/532 ; H01L21/768 ; H01L21/84 ; H01L21/762 ; H01L21/3205 ; H01L21/321 ; H01L29/06 ; H01L21/74

Abstract:
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.
Public/Granted literature
- US20160284731A1 EFFICIENT BURIED OXIDE LAYER INTERCONNECT SCHEME Public/Granted day:2016-09-29
Information query
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