A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.