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公开(公告)号：US20180323189A1
公开(公告)日：2018-11-08
申请号：US16022263
申请日：2018-06-28
发明人： Wolfgang Werner
IPC分类号： H01L27/06 , H01L29/66 , H01L29/78 , H01L29/872 , H01L29/10 , H01L29/739 , H01L29/20 , H01L29/165 , H01L29/16 , H01L29/04 , H01L29/808 , H01L29/267 , H01L29/861
CPC分类号： H01L27/0629 , H01L29/04 , H01L29/1095 , H01L29/1604 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/267 , H01L29/66068 , H01L29/66431 , H01L29/66734 , H01L29/66893 , H01L29/66909 , H01L29/66924 , H01L29/7395 , H01L29/78 , H01L29/7805 , H01L29/7806 , H01L29/7813 , H01L29/8083 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.
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2.发明申请Method for Manufacturing a Semiconductor Substrate, and Method for Manufacturing Semiconductor Devices Integrated in a Semiconductor Substrate 有权半导体基板的制造方法以及集成在半导体基板中的半导体器件的制造方法公开(公告)号：US20140087541A1
公开(公告)日：2014-03-27
申请号：US13628301
申请日：2012-09-27
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/02005 , H01L21/02381 , H01L21/02428 , H01L21/02529 , H01L21/0254 , H01L21/02565 , H01L21/02658 , H01L21/02667 , H01L21/304 , H01L21/3247 , H01L21/76259 , H01L21/7806
摘要： A method of manufacturing a semiconductor substrate includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, and forming, when seen in a cross-section perpendicular to the first surface, cavities in the semiconductor wafer at a first distance from the first surface. The cavities are laterally spaced from each other by partition walls formed by semiconductor material of the wafer. The cavities form a separation region. The method further includes forming a semiconductor layer on the first surface of the semiconductor wafer, and breaking at least some of the partition walls by applying mechanical impact to the partition walls to split the semiconductor wafer along the separation region.
摘要翻译： 一种制造半导体衬底的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体晶片，并且当在垂直于第一表面的横截面中观察时，形成半导体晶片中的第一距离 从第一个表面。 这些空腔通过由晶片的半导体材料形成的分隔壁彼此横向隔开。 空腔形成分离区域。 该方法还包括在半导体晶片的第一表面上形成半导体层，并通过对分隔壁施加机械冲击来破坏至少一些分隔壁，以沿着分离区域分裂半导体晶片。
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公开(公告)号：US20130049176A1
公开(公告)日：2013-02-28
申请号：US13652772
申请日：2012-10-16
IPC分类号： H01L29/36
CPC分类号： H01L21/26506 , H01L21/263 , H01L21/3242
摘要： A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.
摘要翻译： 一种制造半导体的方法包括提供具有第一侧和第二侧的p掺杂半导体本体; 通过第一侧将半导体本体中的质子注入半导体本体的目标深度; 将半导体主体的第一侧接合到载体基板; 通过加热所述半导体本体从而在所述半导体本体中形成pn结，形成在所述半导体本体中的n掺杂区; 以及移除所述半导体本体的所述第二侧至少与在所述pn结处跨过的空间电荷区域一样远。
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公开(公告)号：US10461074B2
公开(公告)日：2019-10-29
申请号：US16022263
申请日：2018-06-28
发明人： Wolfgang Werner
IPC分类号： H01L29/66 , H01L27/06 , H01L29/872 , H01L29/78 , H01L29/267 , H01L29/808 , H01L29/04 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/861 , H01L29/10 , H01L29/739
摘要： According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.
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公开(公告)号：US10032767B2
公开(公告)日：2018-07-24
申请号：US14715996
申请日：2015-05-19
发明人： Wolfgang Werner
IPC分类号： H01L27/06 , H01L29/66 , H01L29/872 , H01L29/78 , H01L29/267 , H01L29/808 , H01L29/04 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/861 , H01L29/10 , H01L29/739
摘要： According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.
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公开(公告)号：US08946872B2
公开(公告)日：2015-02-03
申请号：US13652772
申请日：2012-10-16
IPC分类号： H01L29/36 , H01L21/265 , H01L21/324 , H01L21/263
CPC分类号： H01L21/26506 , H01L21/263 , H01L21/3242
摘要： A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.
摘要翻译： 一种制造半导体的方法包括提供具有第一侧和第二侧的p掺杂半导体本体; 通过第一侧将半导体本体中的质子注入半导体本体的目标深度; 将半导体主体的第一侧接合到载体基板; 通过加热所述半导体本体从而在所述半导体本体中形成pn结，形成在所述半导体本体中的n掺杂区; 以及移除所述半导体本体的所述第二侧至少与在所述pn结处跨过的空间电荷区域一样远。
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公开(公告)号：US20160141405A1
公开(公告)日：2016-05-19
申请号：US14540535
申请日：2014-11-13
发明人： Wolfgang Werner , Frank Kahlmann , Franz Hirler
IPC分类号： H01L29/778 , H01L29/66 , H01L29/40
CPC分类号： H01L29/7786 , H01L29/0623 , H01L29/0634 , H01L29/0657 , H01L29/0843 , H01L29/2003 , H01L29/205 , H01L29/407 , H01L29/42316 , H01L29/43 , H01L29/66431 , H01L29/66462
摘要： A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.
摘要翻译： 晶体管包括源极，与源极间隔开的漏极，以及具有用于连接源极和漏极的二维电荷载流体通道的异质结构体。 晶体管还包括设置在源极和漏极之间的半导体场板。 半导体场板被配置为当晶体管处于通道中断的截止状态并且阻断电压施加到漏极时，至少部分地平衡漏极中的电荷。 由半导体场板提供的平衡电荷均匀分布在半导体场板的平面或体积上。 本文描述了各种半导体场板配置和相应的制造方法。
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公开(公告)号：US20150249082A1
公开(公告)日：2015-09-03
申请号：US14715996
申请日：2015-05-19
发明人： Wolfgang Werner
IPC分类号： H01L27/06 , H01L29/20 , H01L29/165 , H01L29/808 , H01L29/10 , H01L29/872 , H01L29/78 , H01L29/739 , H01L29/16 , H01L29/267
CPC分类号： H01L27/0629 , H01L29/04 , H01L29/1095 , H01L29/1604 , H01L29/1608 , H01L29/165 , H01L29/2003 , H01L29/267 , H01L29/66068 , H01L29/66431 , H01L29/66734 , H01L29/66893 , H01L29/66909 , H01L29/66924 , H01L29/7395 , H01L29/78 , H01L29/7805 , H01L29/7806 , H01L29/7813 , H01L29/8083 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.
摘要翻译： 根据半导体器件的实施例，半导体器件包括具有主表面的半导体本体，半导体本体包括第一带隙材料的漂移区，漂移区为第一导电类型，并且金属化布置 在主表面。 在与主表面基本正交的横截面中，半导体本体还包括直接邻接漂移区和金属化的第一带隙材料的接触区域和具有第二带隙材料的阳极区域， 比第一带隙材料低的带隙。 接触区域是第二导电类型。 阳极区域与金属化部分欧姆接触并与漂移区域形成异质结。
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公开(公告)号：US08975640B2
公开(公告)日：2015-03-10
申请号：US13872391
申请日：2013-04-29
发明人： Wolfgang Werner
IPC分类号： H01L29/15 , H01L29/778 , H01L29/20 , H01L29/66
CPC分类号： H01L29/778 , H01L29/0619 , H01L29/1029 , H01L29/1066 , H01L29/165 , H01L29/2003 , H01L29/267 , H01L29/66431 , H01L29/66462 , H01L29/7783 , H01L29/7786 , H01L29/8611
摘要： A heterojunction semiconductor device having a semiconductor body is provided. The semiconductor body includes a first semiconductor region comprising aluminum gallium nitride, a second semiconductor region comprising gallium nitride and forming a heterojunction with the first semiconductor region, an n-type third semiconductor region, a p-type fourth semiconductor region forming a first rectifying junction with the third semiconductor region, and an n-type seventh semiconductor region adjoining the heterojunction formed between the first semiconductor region and the second semiconductor region. The first rectifying junction forms a rectifying junction of a transistor structure which is in ohmic contact with the seventh semiconductor region. Further, a method for producing such a heterojunction semiconductor device is provided.
摘要翻译： 提供了具有半导体本体的异质结半导体器件。 半导体本体包括包括氮化镓铝的第一半导体区域，包含氮化镓并与第一半导体区域形成异质结的第二半导体区域，n型第三半导体区域，形成第一整流结的p型第四半导体区域 与第三半导体区域以及邻接在第一半导体区域和第二半导体区域之间形成的异质结的n型第七半导体区域。 第一整流结形成与第七半导体区域欧姆接触的晶体管结构的整流结。 此外，提供了一种用于制造这种异质结半导体器件的方法。
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公开(公告)号：US09590087B2
公开(公告)日：2017-03-07
申请号：US14540535
申请日：2014-11-13
发明人： Wolfgang Werner , Frank Kahlmann , Franz Hirler
IPC分类号： H01L29/778 , H01L29/40 , H01L29/66 , H01L29/43 , H01L29/06 , H01L29/205 , H01L29/423 , H01L29/08 , H01L29/20
CPC分类号： H01L29/7786 , H01L29/0623 , H01L29/0634 , H01L29/0657 , H01L29/0843 , H01L29/2003 , H01L29/205 , H01L29/407 , H01L29/42316 , H01L29/43 , H01L29/66431 , H01L29/66462
摘要： A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.
摘要翻译： 晶体管包括源极，与源极间隔开的漏极，以及具有用于连接源极和漏极的二维电荷载流体通道的异质结构体。 晶体管还包括设置在源极和漏极之间的半导体场板。 半导体场板被配置为当晶体管处于通道中断的截止状态并且阻断电压施加到漏极时，至少部分地平衡漏极中的电荷。 由半导体场板提供的平衡电荷均匀分布在半导体场板的平面或体积上。 本文描述了各种半导体场板配置和相应的制造方法。
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