- Patent Title: Electronic package with narrow-factor via including finish layer
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Application No.: US14456606Application Date: 2014-08-11
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Publication No.: US09603247B2Publication Date: 2017-03-21
- Inventor: Rajasekaran Swaminathan , Sairam Agraharam , Amruthavalli Pallavi Alur , Ram Viswanath , Wei-Lun Kane Jen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H05K1/09
- IPC: H05K1/09 ; H05K1/11 ; H05K3/24 ; H01L23/00 ; H05K3/40

Abstract:
This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.
Public/Granted literature
- US20160044786A1 ELECTRONIC PACKAGE WITH NARROW-FACTOR VIA INCLUDING FINISH LAYER Public/Granted day:2016-02-11
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