公开(公告)号：US10916486B2

公开(公告)日：2021-02-09

申请号：US16335527

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Chi-Mon Chen ,  Robert Alan May ,  Amanda E. Schuckman ,  Wei-Lun Kane Jen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L21/56 ,  H01L23/367

Abstract: Various embodiments disclosed relate to semiconductor device and method of making the same using functional silanes. In various embodiments, the present invention provides a semiconductor device including a silicon die component having a first silica surface. The semiconductor device includes a dielectric layer having a second surface generally facing the first silica surface. The semiconductor device includes an interface defined between the first surface and the second surface. The semiconductor device also includes a silane based adhesion promoter layer disposed within the junction and bonded to at least one of the first silica surface and the dielectric layer second surface.

公开(公告)号：US20190019755A1

公开(公告)日：2019-01-17

申请号：US16135695

申请日：2018-09-19

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/13 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/46

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US20170125349A1

公开(公告)日：2017-05-04

申请号：US15350393

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/683 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US20160329274A1

公开(公告)日：2016-11-10

申请号：US14778987

申请日：2014-12-22

Applicant: INTEL CORPORATION

Inventor： Wei-Lun Kane Jen ,  Padam Jain ,  Dilan Seneviratne ,  Chi-Mon Chen

IPC: H01L23/498 ,  H05K1/18 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00

CPC classification number: H05K1/0271 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0014 ,  H05K3/0044 ,  H05K2201/0191 ,  H05K2201/05 ,  H05K2203/0278 ,  H05K2203/085 ,  H01L2924/00

Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

Abstract translation: 所公开的实施例包括用于半导体封装的多层衬底。 衬底可以包括第一层，第一层具有xy平面，第一侧上的各个位置具有低于第一侧面xy平面的第一侧面距离，第二侧面具有第二面xy平面和各个位置 在第二侧上可以具有在第二侧面xy平面下方的第二侧面距离; 以及第二层，其具有耦合到第一层的第二侧的第一侧和与第二层的第一侧相对的第二侧，其中第二层上的各个位置处的第二层的厚度可以由 第一侧距离加上第二边距离。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12014989B2

公开(公告)日：2024-06-18

申请号：US18091048

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US20210280517A1

公开(公告)日：2021-09-09

申请号：US16322423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US09603247B2

公开(公告)日：2017-03-21

申请号：US14456606

申请日：2014-08-11

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Sairam Agraharam ,  Amruthavalli Pallavi Alur ,  Ram Viswanath ,  Wei-Lun Kane Jen

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/24 ,  H01L23/00 ,  H05K3/40

CPC classification number: H05K1/112 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/1403 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16501 ,  H01L2224/29082 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81464 ,  H01L2224/83101 ,  H01L2224/83191 ,  H05K1/09 ,  H05K1/113 ,  H05K1/185 ,  H05K3/243 ,  H05K3/244 ,  H05K3/4046 ,  H05K2201/09472 ,  H05K2201/10189 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079

Abstract: This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.

公开(公告)号：US10103105B2

公开(公告)日：2018-10-16

申请号：US15350393

申请日：2016-11-14

Applicant: Intel Corporation

Inventor： Mihir K Roy ,  Stefanie M Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

公开(公告)号：US09548264B2

公开(公告)日：2017-01-17

申请号：US14992535

申请日：2016-01-11

Applicant: Intel Corporation

Inventor： Mihir K. Roy ,  Stefanie M. Lotz ,  Wei-Lun Kane Jen

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/14 ,  H01L23/538 ,  H01L21/48 ,  H05K1/03 ,  H05K1/14 ,  H05K3/46 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。

公开(公告)号：US12040276B2

公开(公告)日：2024-07-16

申请号：US17888177

申请日：2022-08-15

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.