Invention Grant
- Patent Title: Chained bus method
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Application No.: US14053255Application Date: 2013-10-14
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Publication No.: US09606885B2Publication Date: 2017-03-28
- Inventor: Victor Tsai , William Henry Radke , Bob Leibowitz
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F12/00 ; G06F11/30 ; G06F13/42

Abstract:
Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
Public/Granted literature
- US20140040507A1 CHAINED BUS METHOD AND DEVICE Public/Granted day:2014-02-06
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