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公开(公告)号：US20170199828A1
公开(公告)日：2017-07-13
申请号：US15470590
申请日：2017-03-27
Applicant: Micron Technology, Inc
Inventor： Victor Tsai , William Henry Radke , Bob Leibowitz
CPC classification number: G06F12/1081 , G06F3/007 , G06F11/3034 , G06F13/16 , G06F13/28 , G06F13/4063 , G06F13/4208 , G06F13/4234
Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
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公开(公告)号：US20160253237A1
公开(公告)日：2016-09-01
申请号：US15148321
申请日：2016-05-06
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
CPC classification number: G06F11/1068 , G06F11/1016 , G06F11/1048 , G06F11/1072 , G11C29/52 , H03M13/116 , H03M13/2906 , H03M13/356
Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US09336086B2
公开(公告)日：2016-05-10
申请号：US14600800
申请日：2015-01-20
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
CPC classification number: G06F11/1068 , G06F11/1016 , G06F11/1048 , G06F11/1072 , G11C29/52 , H03M13/116 , H03M13/2906 , H03M13/356
Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US08938657B2
公开(公告)日：2015-01-20
申请号：US14153703
申请日：2014-01-13
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
CPC classification number: H03M13/05 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/00
Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.
Abstract translation: 描述存储器件和方法，例如在多个存储器件位置之间混合数据和相关联的纠错码块的存储器件和方法。 示例包括在多个存储器块之间进行混合，在存储器页之间进行混合，存储器芯片之间的混合以及存储器模块之间 在所选择的示例中，存储器块和相关联的纠错码在多级存储器件层级之间混合。
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公开(公告)号：US10664411B2
公开(公告)日：2020-05-26
申请号：US15470590
申请日：2017-03-27
Applicant: Micron Technology, Inc.
Inventor： Victor Tsai , William Henry Radke , Bob Leibowitz
Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
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Patent Agency Ranking
公开(公告)号：US20140129906A1
公开(公告)日：2014-05-08
申请号：US14153703
申请日：2014-01-13
Applicant: Micron Technology, Inc.
Inventor： William Henry Radke
CPC classification number: H03M13/05 , G06F11/1008 , G06F11/1012 , G06F11/1072 , G11C29/00
Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.
Abstract translation: 描述存储器件和方法，例如在多个存储器件位置之间混合数据和相关联的纠错码块的存储器件和方法。 示例包括在多个存储器块之间进行混合，在存储器页之间进行混合，存储器芯片之间的混合以及存储器模块之间的混合。 在所选择的示例中，存储器块和相关联的纠错码在多级存储器件层级之间混合。
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公开(公告)号：US20140040507A1
公开(公告)日：2014-02-06
申请号：US14053255
申请日：2013-10-14
Applicant: Micron Technology, Inc.
Inventor： Victor Tsai , William Henry Radke , Bob Leibowitz
IPC: G06F11/30
CPC classification number: G06F12/1081 , G06F3/007 , G06F11/3034 , G06F13/16 , G06F13/28 , G06F13/4063 , G06F13/4208 , G06F13/4234
Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
Abstract translation: 描述和示出了能够在链中配置的存储器件和方法。 在一个配置中，主机使用单个数据输入端口和单个数据输出端口与存储器设备链路进行通信。 描述了将标识符分配给链中的存储器件的方法，其包括检测下游存储器件的存在或不存在。 在所选择的示例中，标识符被顺序地分配给链中的存储设备，直到没有检测到附加的下游存储器设备。
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公开(公告)号：US09646683B2
公开(公告)日：2017-05-09
申请号：US14803918
申请日：2015-07-20
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
CPC classification number: G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.
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公开(公告)号：US09606885B2
公开(公告)日：2017-03-28
申请号：US14053255
申请日：2013-10-14
Applicant: Micron Technology, Inc.
Inventor： Victor Tsai , William Henry Radke , Bob Leibowitz
CPC classification number: G06F12/1081 , G06F3/007 , G06F11/3034 , G06F13/16 , G06F13/28 , G06F13/4063 , G06F13/4208 , G06F13/4234
Abstract: Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.
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公开(公告)号：US09520183B2
公开(公告)日：2016-12-13
申请号：US14707684
申请日：2015-05-08
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
CPC classification number: G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
Abstract translation: 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。
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