- 专利标题: Single wire system clock signal generation
-
申请号: US14546564申请日: 2014-11-18
-
公开(公告)号: US09612609B2公开(公告)日: 2017-04-04
- 发明人: Albert S. Weiner
- 申请人: Atmel Corporation
- 申请人地址: US CA San Jose
- 专利权人: Atmel Corporation
- 当前专利权人: Atmel Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Fish & Richardson P.C.
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F1/22 ; G06F1/32 ; G06F13/42
摘要:
This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.
公开/授权文献
- US20160142201A1 SINGLE WIRE SYSTEM CLOCK SIGNAL GENERATION 公开/授权日:2016-05-19
信息查询