Invention Grant
- Patent Title: Input path matching in pipelined continuous-time analog-to-digital converters
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Application No.: US15068231Application Date: 2016-03-11
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Publication No.: US09614510B2Publication Date: 2017-04-04
- Inventor: Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Goutham Kondapalli; Chares A. Brill; Frank D. Cimino
- Main IPC: H03K5/159
- IPC: H03K5/159 ; H03M3/00 ; H03M1/16

Abstract:
System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
Public/Granted literature
- US20160269045A1 Input Path Matching in Pipelined Continuous-Time Analog-to-Digital Converters Public/Granted day:2016-09-15
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