Invention Grant
- Patent Title: Via structure for optimizing signal porosity
-
Application No.: US15346693Application Date: 2016-11-08
-
Publication No.: US09620452B2Publication Date: 2017-04-11
- Inventor: Xiongfei Meng , Joon Hyung Chung , Yuancheng Christopher Pan
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox LLP
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/535 ; H01L23/522 ; H01L27/06

Abstract:
An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
Public/Granted literature
- US20170053866A1 VIA STRUCTURE FOR OPTIMIZING SIGNAL POROSITY Public/Granted day:2017-02-23
Information query
IPC分类: