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    ON-CHIP SENSOR FOR MEASURING DYNAMIC POWER SUPPLY NOISE OF THE SEMICONDUCTOR CHIP
    1.
    发明申请
    ON-CHIP SENSOR FOR MEASURING DYNAMIC POWER SUPPLY NOISE OF THE SEMICONDUCTOR CHIP 审中-公开
    用于测量半导体芯片动态电源噪声的片上传感器

    公开(公告)号：US20130285696A1

    公开(公告)日：2013-10-31

    申请号：US13928424

    申请日：2013-06-27

    Applicant: QUALCOMM Incorporated

    Inventor： Lew Chua-Eoan ,  Boris Andreev ,  Yuancheng Christopher Pan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

    IPC: G01R31/317

    CPC classification number: G01R31/31721 ,  G01R29/26

    Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

    Abstract translation: 片上传感器测量半导体芯片上的动态电源噪声，如电压下降。 采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。 示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。 原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。 因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

    Low power high resolution oscillator based voltage sensor
    4.
    发明授权
    Low power high resolution oscillator based voltage sensor 有权
    低功耗基于高分辨率振荡器的电压传感器

    公开(公告)号：US09575095B2

    公开(公告)日：2017-02-21

    申请号：US14459208

    申请日：2014-08-13

    Applicant: QUALCOMM Incorporated

    Inventor： Junmou Zhang ,  Chuang Zhang ,  Yuancheng Christopher Pan ,  Nan Chen

    IPC: G01R23/02 ,  G01R19/00 ,  G01R31/28 ,  G01R19/165

    CPC classification number: G01R19/0084 ,  G01R19/16552 ,  G01R23/02 ,  G01R31/282

    Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

    Abstract translation: 本文描述了用于感测芯片上的电压的系统和方法。 在一个实施例中，电压传感器包括耦合到被感测的电压的压控振荡器和多个转换检测器，其中每个转换检测器耦合到振荡器上的不同位置，并且其中每个转换检测器 被配置为在一段时间段内对相应位置的多个转换进行计数。 电压传感器还包括加法器，其被配置为将来自转换检测器的转移数目相加以产生大致与电压成比例的输出值。

    Via structure for optimizing signal porosity
    5.
    发明授权
    Via structure for optimizing signal porosity 有权
    通孔结构，用于优化信号孔隙度

    公开(公告)号：US09520358B2

    公开(公告)日：2016-12-13

    申请号：US14744634

    申请日：2015-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Xiongfei Meng ,  Joon Hyung Chung ,  Yuancheng Christopher Pan

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/06 ,  H01L23/66

    CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/66 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.

    Abstract translation: 包括导电堆叠结构的装置包括在Mx层上的Mx层互连并且在第一轨道上沿第一方向延伸，My层上的My层互连，其中My层是比Mx层低的层， 首先通过耦合在Mx层互连和My层互连之间的堆叠，耦合在Mx层互连和My层互连之间的第二通孔堆叠，在紧邻第一轨道的轨道上沿第一方向延伸的第二Mx层互连 以及在紧邻第一轨道的轨道上沿第一方向延伸的第三M×层互连。 Mx层互连在第二Mx层互连和第三Mx层互连之间。 第二Mx层互连和第三Mx层互连彼此分离。

    LOW POWER HIGH RESOLUTION OSCILLATOR BASED VOLTAGE SENSOR
    6.
    发明申请
    LOW POWER HIGH RESOLUTION OSCILLATOR BASED VOLTAGE SENSOR 有权
    低功率高分辨率振荡器基于电压传感器

    公开(公告)号：US20160047847A1

    公开(公告)日：2016-02-18

    申请号：US14459208

    申请日：2014-08-13

    Applicant: QUALCOMM Incorporated

    Inventor： Junmou Zhang ,  Chuang Zhang ,  Yuancheng Christopher Pan ,  Nan Chen

    IPC: G01R19/00 ,  G01R23/02 ,  G01R31/28

    CPC classification number: G01R19/0084 ,  G01R19/16552 ,  G01R23/02 ,  G01R31/282

    Abstract: Systems and methods for sensing voltage on a chip are described herein. In one embodiment, a voltage sensor comprises a voltage-controlled oscillator coupled to a voltage being sensed, and a plurality of transition detectors, wherein each of the transition detectors is coupled to a different location on the oscillator, and wherein each of the transition detectors is configured to count a number of transitions at the respective location over a time period. The voltage sensor also comprises an adder configured to add the numbers of transitions from the transition detectors to generate an output value that is approximately proportional to the voltage.

    Abstract translation: 本文描述了用于感测芯片上的电压的系统和方法。 在一个实施例中，电压传感器包括耦合到被感测的电压的压控振荡器和多个转换检测器，其中每个转换检测器耦合到振荡器上的不同位置，并且其中每个转换检测器 被配置为在一段时间段内对相应位置的多个转换进行计数。 电压传感器还包括加法器，其被配置为将来自转换检测器的转移数目相加以产生大致与电压成比例的输出值。

    DYNAMIC POWER RAIL CONTROL FOR CLUSTERS OF LOADS
    10.
    发明申请
    DYNAMIC POWER RAIL CONTROL FOR CLUSTERS OF LOADS 有权
    负载集群的动态功率轨迹控制

    公开(公告)号：US20160013643A1

    公开(公告)日：2016-01-14

    申请号：US14327410

    申请日：2014-07-09

    Applicant: QUALCOMM Incorporated

    Inventor： Hee Jun Park ,  Yuancheng Christopher Pan ,  Christopher Kong Yee Chun

    IPC: H02J3/00 ,  G06F1/28

    CPC classification number: H02J3/00 ,  G06F1/28 ,  H02J1/00 ,  H02J1/08 ,  H02J1/102

    Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.

    Abstract translation: 管理电源轨，包括：多个电源轨，每个电源轨耦合到至少一个电源并且被配置为支撑多个类似配置的负载; 以及电力轨控制器，其被配置为基于所述多个类似配置的负载的总功率消耗来合并和分割所述多个电力轨。 电力轨道管理还根据每个轨道的当前负载确定最佳电力轨模式（合并/分割），并调整动态时钟和电压调整策略，每个核心上的工作负载分配以及根据电力轨道的性能限制/节流管理 模式。

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